/gem5/src/dev/alpha/ |
H A D | tsunami_cchip.cc | 78 TsunamiCChip::read(PacketPtr pkt) function in class:TsunamiCChip 80 DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 176 panic("default in cchip read reached, accessing 0x%x\n"); 186 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 371 panic("default in cchip read reached, accessing 0x%x\n");
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/gem5/src/dev/arm/ |
H A D | hdlcd.cc | 194 // Create the DMA engine and read its state from the 236 // read registers and frame buffer 238 HDLcd::read(PacketPtr pkt) function in class:HDLcd 245 "Unhandled read size (address: 0x.4x, size: %u)", 249 DPRINTF(HDLcd, "read register 0x%04x: 0x%x\n", daddr, data); 265 "Unhandled read size (address: 0x.4x, size: %u)", 311 panic("Tried to read HDLCD register that doesn't exist\n", offset); 320 panic("HDLCD VERSION register is read-Only\n"); 332 panic("HDLCD INT_STATUS register is read-Only\n");
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H A D | ufs_device.hh | 106 /** UFS read transaction flow state machine 409 * Keep in mind that for a read-from-disk transaction the host at first a 412 * different read transactions should be placed and then transfers all the 413 * read fragments. It then answers to the original caller with two replies, 505 /** Amount of data read/written */ 559 * Read flash. read the data from the disk image. This function 584 * Finished read. Probe to find out which logic unit finished its 585 * read. This is needed, because multiple units can do transactions 593 * Clear signal. Handle for the host to clear the read complete 654 * should be made at the end of a read transfe [all...] |
H A D | gic_v3_its.hh | 149 Tick read(PacketPtr pkt) override; 165 // Command read/write, (CREADR, CWRITER) 417 * main will firstly read the command from memory and then it will process
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H A D | pl111.cc | 99 // read registers and frame buffer 101 Pl111::read(PacketPtr pkt) function in class:Pl111 103 // use a temporary data since the LCD registers are read/written with 113 DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize()); 203 panic("Tried to read CLCD register at offset %#x that " 220 panic("CLCD controller read size too big?\n"); 232 // use a temporary data since the LCD registers are read/written with 459 // initialization for dma read from frame buffer to dma buffer 538 // schedule the next read based on when the last frame started
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H A D | generic_timer.cc | 356 warn("Ignoring write to read only count register: %s\n", 568 GenericTimerMem::read(PacketPtr pkt) function in class:GenericTimerMem
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H A D | vgic.cc | 71 VGic::read(PacketPtr pkt) function in class:VGic 105 DPRINTF(VGIC, "VGIC VCPU read register %#x\n", daddr); 134 panic("VGIC VCPU read of bad address %#x\n", daddr); 150 DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); 218 warn_once("VGIC GICH_APR read!\n"); 230 panic("VGIC HVCtrl read of bad address %#x\n", daddr); 409 // (Cached so that regs can read them without messing about again)
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H A D | gic_v3_redistributor.cc | 90 Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access) function in class:Gicv3Redistributor 379 panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
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H A D | ufs_device.cc | 60 * transaction flow, data write transfer and data read transfer. The 153 * Synchronize Cache and buffer read/write could not be tested yet 303 * read the capacity of the device 603 * less trivial than normal read. Size is in bytes instead 688 * read from the flashdisk 695 /** read from image, and get to memory */ 697 flashDisk->read(&(readaddr[SectorSize*count]), (offset / 791 .desc("Most up to date length of the read SSD queue") 798 /** Amount of data read/written */ 801 .desc("Number of bytes read fro 929 UFSHostDevice::read(PacketPtr pkt) function in class:UFSHostDevice [all...] |
/gem5/configs/example/ |
H A D | fs.py | 79 return open(options.command_line_file).read().strip()
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H A D | read_config.py | 39 # previous gem5 run to be read in and instantiated. 43 # simulation control) to read pre-described systems from config scripts 421 self.parser.read(config_file)
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/gem5/src/dev/ |
H A D | dma_device.cc | 343 buffer.read(dst, len);
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/gem5/src/dev/sparc/ |
H A D | iob.cc | 77 Iob::read(PacketPtr pkt) function in class:Iob
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/gem5/ext/ply/ply/ |
H A D | cpp.py | 753 data = open(iname,"r").read() 880 input = f.read()
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H A D | lex.py | 1018 data = f.read() 1022 data = sys.stdin.read()
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/gem5/src/systemc/tests/systemc/examples/aes/ |
H A D | aes.cpp | 302 t_In_wire = In_wire.read(); 732 t_In_wire = In_wire.read();
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/gem5/src/systemc/tests/systemc/misc/stars/star108761/ |
H A D | star108761.cpp | 1098 tmp = comp_mux(inp.read());
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/gem5/src/dev/pci/ |
H A D | copy_engine.cc | 169 CopyEngine::read(PacketPtr pkt) function in class:CopyEngine 189 /// Handle read of register here
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/gem5/src/python/m5/util/ |
H A D | jobfile.py | 421 exec(compile(open(filename).read(), filename, 'exec'), data)
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/gem5/src/sim/ |
H A D | pseudo_inst.cc | 517 int bytes = ::read(fd, p, len);
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 191 X86ISA::Interrupts::read(PacketPtr pkt) function in class:X86ISA::Interrupts 431 // The Local APIC Version register is read only. 586 //Local APIC Current Count register is read only.
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.cpp | 60 // execute instruction /read instr mem 63 // | \read data mem 73 // so these memory accesses are just read and write in internal memory 118 // read new line at each loop ------------------------------------------ 1173 mem_rd_n.write(0); // read RAM 1196 mem_rd_n.write(0); // read RAM 1214 // read/write enable <- 1 when stretch>0 1218 // read value 1219 *result = mem_data_in.read().to_uint(); 1220 // reset read enabl [all...] |
/gem5/src/dev/net/ |
H A D | sinic.cc | 215 * I/O read of device register 218 Device::read(PacketPtr pkt) function in class:Sinic::Device 233 if (!info.read) 234 panic("read %s (write only): " 238 panic("read %s (invalid size): " 258 "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n", 270 * IPR read of device register 279 if (!info.read) 282 DPRINTF(EthernetPIO, "IPR read %s: cpu=%d da=%#x\n", 293 DPRINTF(EthernetPIO, "IPR read [all...] |
/gem5/src/dev/storage/ |
H A D | ide_disk.cc | 209 // Device registers read/write 223 panic("Data read of unsupported size %d.\n", size); 413 .desc("Number of DMA read transactions (not PRD).") 578 uint32_t bytesRead = image->read(data, sector); 581 panic("Can't read from %s. Only %d of %d read. errno=%d\n", 707 dmaRead = true; // a write to the disk is a DMA read from memory
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/async_reset/ |
H A D | async_reset.cpp | 512 clk.write( !clk.read() );
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