Searched refs:queue (Results 76 - 80 of 80) sorted by relevance

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/gem5/src/cpu/o3/
H A Dlsq.hh48 #include <queue>
122 * DcachePort class for the load/store queue.
156 * As this CPU requires snooping to maintain the load store queue
899 /** Returns the head index of the load queue for a specific thread. */
902 /** Returns the sequence number of the head of the load queue. */
909 /** Returns the head index of the store queue. */
912 /** Returns the sequence number of the head of the store queue. */
924 /** Returns the total number of loads in the load queue. */
929 /** Returns the total number of stores in the store queue. */
H A Diew_impl.hh51 #include <queue>
104 // Instruction queue needs the queue between issue and execute.
353 // Instruction queue also needs main time buffer.
363 // Setup wire to read information from rename queue.
627 // being added to the queue to commit without being processed by
645 // Add finished instruction to queue to commit.
963 // Obtain instructions from skid buffer if unblocking, or queue from rename
965 std::queue<DynInstPtr> &insts_to_dispatch =
976 // queue
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H A Dfetch_impl.hh52 #include <queue>
798 // Empty fetch queue
951 // Send instructions enqueued into the fetch queue to decode.
972 "from fetch queue. Fetch queue size: %i.\n",
1141 // Write the instruction to the first slot in the queue
1146 DPRINTF(Fetch, "[tid:%i] Fetch queue entry created (%i/%i).\n",
1244 // queue heading to decode.
1246 DPRINTF(Fetch, "[tid:%i] Adding instructions to queue to "
/gem5/src/cpu/
H A Dbase_dyn_inst.hh174 std::queue<InstResult> instResult;
229 /** Load queue index. */
233 /** Store queue index. */
611 /** Return the size of the instResult queue. */
614 /** Pops a result off the instResult queue.
627 /** Pushes a result onto the instResult queue. */
/gem5/src/mem/cache/
H A Dbase.cc72 : QueuedSlavePort(_name, _cache, queue),
73 queue(*_cache, *this, true, _label),
112 // the MSHR queue has no reserve entries as we check the MSHR
113 // queue on every single allocation, whereas the write queue has
232 // queue the packet for deletion, as the sending cache is
510 // while we deallocate an mshr from the queue we still have to
723 // Check both MSHR queue and write buffer for potential requests,
732 // need to search MSHR queue for conflicting earlier miss.
772 // If we have a miss queue slo
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