Searched refs:pkt (Results 201 - 225 of 375) sorted by relevance

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/gem5/src/arch/arm/
H A Dstage2_mmu.cc80 Packet pkt = Packet(req, MemCmd::ReadReq); local
81 pkt.dataStatic(data);
83 port.sendFunctional(&pkt);
85 port.sendAtomic(&pkt);
87 assert(!pkt.isError());
/gem5/src/mem/cache/prefetch/
H A Dqueued.hh65 PacketPtr pkt; member in struct:QueuedPrefetcher::DeferredPacket
82 int32_t prio) : owner(o), pfInfo(pfi), tick(t), pkt(nullptr),
182 void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) override;
184 void insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority);
246 PacketPtr pkt);
/gem5/src/cpu/simple/
H A Datomic.hh106 virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt);
125 bool recvTimingResp(PacketPtr pkt) argument
154 virtual Tick recvAtomicSnoop(PacketPtr pkt);
155 virtual void recvFunctionalSnoop(PacketPtr pkt);
183 void threadSnoop(PacketPtr pkt, ThreadID sender);
H A Dtiming.hh135 void threadSnoop(PacketPtr pkt, ThreadID sender);
150 bool handleReadPacket(PacketPtr pkt);
175 PacketPtr pkt; member in struct:TimingSimpleCPU::TimingCPUPort::TickEvent
178 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
197 virtual bool recvTimingResp(PacketPtr pkt);
231 virtual void recvTimingSnoopReq(PacketPtr pkt);
232 virtual void recvFunctionalSnoop(PacketPtr pkt);
234 virtual bool recvTimingResp(PacketPtr pkt);
302 void completeDataAccess(PacketPtr pkt);
330 Packet *pkt; member in struct:TimingSimpleCPU::IprEvent
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/gem5/src/dev/x86/
H A Di8042.cc126 X86ISA::I8042::read(PacketPtr pkt) argument
128 assert(pkt->getSize() == 1);
129 Addr addr = pkt->getAddr();
133 pkt->setLE<uint8_t>(data);
136 pkt->setLE<uint8_t>((uint8_t)statusReg);
140 pkt->makeAtomicResponse();
145 X86ISA::I8042::write(PacketPtr pkt) argument
147 assert(pkt->getSize() == 1);
148 Addr addr = pkt->getAddr();
149 uint8_t data = pkt
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/gem5/src/dev/arm/
H A Dgic_v2.cc113 GicV2::read(PacketPtr pkt) argument
115 const Addr addr = pkt->getAddr();
118 return readDistributor(pkt);
120 return readCpu(pkt);
122 panic("Read to unknown address %#x\n", pkt->getAddr());
127 GicV2::write(PacketPtr pkt) argument
129 const Addr addr = pkt->getAddr();
132 return writeDistributor(pkt);
134 return writeCpu(pkt);
136 panic("Write to unknown address %#x\n", pkt
140 readDistributor(PacketPtr pkt) argument
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H A Dgpu_nomali.cc149 NoMaliGpu::read(PacketPtr pkt) argument
151 assert(pkt->getAddr() >= pioAddr);
152 const Addr addr(pkt->getAddr() - pioAddr);
153 const unsigned size(pkt->getSize());
163 pkt->setLE<uint32_t>(readReg(addr));
164 pkt->makeResponse();
170 NoMaliGpu::write(PacketPtr pkt) argument
172 assert(pkt->getAddr() >= pioAddr);
173 const Addr addr(pkt->getAddr() - pioAddr);
174 const unsigned size(pkt
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H A Dhdlcd.cc238 HDLcd::read(PacketPtr pkt) argument
240 assert(pkt->getAddr() >= pioAddr &&
241 pkt->getAddr() < pioAddr + pioSize);
243 const Addr daddr(pkt->getAddr() - pioAddr);
244 panic_if(pkt->getSize() != 4,
246 daddr, pkt->getSize());
251 pkt->setLE<uint32_t>(data);
252 pkt->makeAtomicResponse();
258 HDLcd::write(PacketPtr pkt) argument
260 assert(pkt
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H A Dpl111.cc101 Pl111::read(PacketPtr pkt) argument
108 assert(pkt->getAddr() >= pioAddr &&
109 pkt->getAddr() < pioAddr + pioSize);
111 Addr daddr = pkt->getAddr() - pioAddr;
113 DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize());
186 if (readId(pkt, AMBA_ID, pioAddr)) {
188 data = pkt->getLE<uint32_t>();
209 switch(pkt->getSize()) {
211 pkt->setLE<uint8_t>(data);
214 pkt
230 write(PacketPtr pkt) argument
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H A Dgpu_nomali.hh65 Tick read(PacketPtr pkt) override;
66 Tick write(PacketPtr pkt) override;
/gem5/src/gpu-compute/
H A Dcompute_unit.hh257 void fetch(PacketPtr pkt, Wavefront *wavefront);
284 void sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
285 void sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt);
289 void handleMemPacket(PacketPtr pkt, int memport_index);
290 bool processTimingPacket(PacketPtr pkt);
291 void processFetchReturn(PacketPtr pkt);
444 void processMemReqEvent(PacketPtr pkt);
445 EventFunctionWrapper *createMemReqEvent(PacketPtr pkt);
447 void processMemRespEvent(PacketPtr pkt);
448 EventFunctionWrapper *createMemRespEvent(PacketPtr pkt);
457 recvAtomic(PacketPtr pkt) argument
458 recvFunctional(PacketPtr pkt) argument
498 recvAtomic(PacketPtr pkt) argument
499 recvFunctional(PacketPtr pkt) argument
554 recvAtomic(PacketPtr pkt) argument
555 recvFunctional(PacketPtr pkt) argument
593 recvAtomic(PacketPtr pkt) argument
594 recvFunctional(PacketPtr pkt) argument
656 recvAtomic(PacketPtr pkt) argument
659 recvFunctional(PacketPtr pkt) argument
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H A Dgpu_tlb.cc1033 GpuTLB::issueTLBLookup(PacketPtr pkt) argument
1035 assert(pkt);
1036 assert(pkt->senderState);
1038 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1042 safe_cast<TranslationState*>(pkt->senderState);
1060 const RequestPtr &tmp_req = pkt->req;
1097 new TLBEvent(this, virt_page_addr, lookup_outcome, pkt);
1116 outcome(tlb_outcome), pkt(_pkt)
1125 GpuTLB::pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, argument
1129 uint32_t flags = pkt
1159 handleTranslationReturn(Addr virt_page_addr, tlbOutcome tlb_outcome, PacketPtr pkt) argument
1244 translationReturn(Addr virtPageAddr, tlbOutcome outcome, PacketPtr pkt) argument
1387 recvTimingReq(PacketPtr pkt) argument
1410 handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome tlb_outcome) argument
1480 recvFunctional(PacketPtr pkt) argument
1615 recvTimingResp(PacketPtr pkt) argument
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H A Dtlb_coalescer.cc142 TLBCoalescer::updatePhysAddresses(PacketPtr pkt) argument
144 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
150 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
163 Addr phys_page_paddr = pkt->req->getPaddr();
207 // Translation is done - Convert to a response pkt if necessary and
230 TLBCoalescer::CpuSidePort::recvTimingReq(PacketPtr pkt) argument
240 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
249 // multiple uncoalesced reqs(pkts) but just a single pkt.
263 DPRINTF(GPUTLB, "receiving pkt w/ req_cnt %d\n", req_cnt);
285 // see if we can coalesce the incoming pkt wit
335 recvFunctional(PacketPtr pkt) argument
371 recvTimingResp(PacketPtr pkt) argument
389 recvFunctional(PacketPtr pkt) argument
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/gem5/src/arch/x86/
H A Dmemhelpers.hh54 getMem(PacketPtr pkt, uint64_t &mem, unsigned dataSize, argument
59 mem = pkt->getLE<uint8_t>();
62 mem = pkt->getLE<uint16_t>();
65 mem = pkt->getLE<uint32_t>();
68 mem = pkt->getLE<uint64_t>();
79 getPackedMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize) argument
81 std::array<T, N> real_mem = pkt->getLE<std::array<T, N> >();
88 getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize, argument
93 getPackedMem<uint32_t, N>(pkt, mem, dataSize);
96 getPackedMem<uint64_t, N>(pkt, me
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/gem5/src/mem/cache/
H A Dcache_blk.hh311 void trackLoadLocked(PacketPtr pkt) argument
313 assert(pkt->isLLSC());
316 if (l->intersects(pkt->req))
322 lockList.emplace_front(pkt->req);
394 bool checkWrite(PacketPtr pkt) argument
396 assert(pkt->isWrite());
399 if (!pkt->isLLSC() && lockList.empty())
402 const RequestPtr &req = pkt->req;
404 if (pkt->isLLSC()) {
411 if (l->matches(pkt
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H A Dmshr_queue.hh90 * @param pkt The original miss.
99 MSHR *allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
/gem5/src/dev/pci/
H A Dcopy_engine.hh101 virtual Tick read(PacketPtr pkt) argument
103 virtual Tick write(PacketPtr pkt) argument
106 void channelRead(PacketPtr pkt, Addr daddr, int size);
107 void channelWrite(PacketPtr pkt, Addr daddr, int size);
199 Tick read(PacketPtr pkt) override;
200 Tick write(PacketPtr pkt) override;
/gem5/src/mem/ruby/system/
H A DGPUCoalescer.hh66 PacketPtr pkt; member in struct:GPUCoalescerRequest
72 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
79 RequestDesc(PacketPtr pkt, RubyRequestType p_type, RubyRequestType s_type) argument
80 : pkt(pkt), primaryType(p_type), secondaryType(s_type)
84 RequestDesc() : pkt(nullptr), primaryType(RubyRequestType_NULL),
89 PacketPtr pkt; member in class:RequestDesc
162 virtual RequestStatus makeRequest(PacketPtr pkt);
188 void insertKernel(int wavefront_id, PacketPtr pkt);
230 virtual void issueRequest(PacketPtr pkt, RubyRequestTyp
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/gem5/src/mem/ruby/network/garnet2.0/
H A DCrossbarSwitch.hh61 uint32_t functionalWrite(Packet *pkt);
H A Dflit.cc82 flit::functionalWrite(Packet *pkt) argument
85 return msg->functionalWrite(pkt);
/gem5/src/mem/cache/tags/
H A Dcompressed_tags.hh117 * @param pkt Packet holding the address to update
120 void insertBlock(const PacketPtr pkt, CacheBlk *blk) override;
/gem5/src/systemc/tlm_bridge/
H A Dtlm_to_gem5.hh101 recvTimingResp(PacketPtr pkt) override
103 return bridge.recvTimingResp(pkt);
139 void destroyPacket(PacketPtr pkt);
159 bool recvTimingResp(PacketPtr pkt);
/gem5/src/arch/sparc/
H A Dtlb.cc861 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) argument
863 Addr va = pkt->getAddr();
864 ASI asi = (ASI)pkt->req->getArchFlags();
868 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
875 pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
880 pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
883 pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
890 pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
895 pkt
1046 doMmuRegWrite(ThreadContext *tc, Packet *pkt) argument
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/gem5/src/mem/
H A Dpacket.hh661 * @pkt The packet that we will copy flags from
663 void copyResponderFlags(const PacketPtr pkt);
726 void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; } argument
842 Packet(const PacketPtr pkt, bool clear_flags, bool alloc_data) argument
843 : cmd(pkt->cmd), id(pkt->id), req(pkt->req),
845 addr(pkt
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/gem5/src/mem/ruby/network/simple/
H A DSimpleNetwork.hh73 bool functionalRead(Packet *pkt);
74 uint32_t functionalWrite(Packet *pkt);

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