Searched refs:pkt (Results 151 - 175 of 375) sorted by relevance

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/gem5/src/mem/ruby/system/
H A DRubyPortProxy.cc57 RubyPortProxy::makeRequest(PacketPtr pkt) argument
/gem5/src/dev/arm/
H A Dtimer_a9global.hh132 void read(PacketPtr pkt, Addr daddr);
135 void write(PacketPtr pkt, Addr daddr);
162 * @param pkt The memory request.
165 Tick read(PacketPtr pkt) override;
169 * @param pkt The memory request.
172 Tick write(PacketPtr pkt) override;
H A Dtimer_sp804.hh119 void read(PacketPtr pkt, Addr daddr);
122 void write(PacketPtr pkt, Addr daddr);
150 * @param pkt The memory request.
153 Tick read(PacketPtr pkt) override;
157 * @param pkt The memory request.
160 Tick write(PacketPtr pkt) override;
H A Dgic_v3.cc100 Gicv3::read(PacketPtr pkt) argument
102 const Addr addr = pkt->getAddr();
103 const size_t size = pkt->getSize();
104 bool is_secure_access = pkt->isSecure();
115 pkt->req->contextId(), daddr, size, is_secure_access, resp);
125 redist->processorNumber(), pkt->req->contextId(), daddr, size,
131 pkt->setUintX(resp, LittleEndianByteOrder);
132 pkt->makeAtomicResponse();
137 Gicv3::write(PacketPtr pkt) argument
139 const size_t size = pkt
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/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc73 PacketPtr pkt = new Packet(req, cmd); local
74 pkt->allocate();
76 if (port->sendTimingReq(pkt)) {
84 delete pkt;
/gem5/src/mem/cache/
H A Dwrite_queue.hh78 * @param pkt The original write.
87 PacketPtr pkt, Tick when_ready, Counter order);
H A Dmshr.hh184 * @param pkt Packet considered for the flag update
186 * @param alloc_on_fill Whether the pkt would allocate on a fill
188 void updateFlags(PacketPtr pkt, Target::Source source,
228 * @param pkt Packet considered for adding
230 void updateWriteFlags(PacketPtr pkt) { argument
242 bool can_merge_write = pkt->isWrite() &&
243 ((pkt->req->getFlags() & noMergeFlags) == 0);
246 auto offset = pkt->getOffset(blkSize);
248 std::fill(begin, begin + pkt->getSize(), true);
269 * @param pkt Packe
339 PacketPtr pkt = targets.front().pkt; local
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H A Dqueue.hh184 bool trySatisfyFunctional(PacketPtr pkt) argument
186 pkt->pushLabel(label);
188 if (entry->matchBlockAddr(pkt) &&
189 entry->trySatisfyFunctional(pkt)) {
190 pkt->popLabel();
194 pkt->popLabel();
/gem5/src/dev/
H A Ddma_device.cc68 DmaPort::handleResp(PacketPtr pkt, Tick delay) argument
71 assert(pkt->isResponse());
74 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
79 pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(),
89 state->numBytes += pkt->req->getSize();
103 delete pkt;
111 DmaPort::recvTimingResp(PacketPtr pkt) argument
114 assert(pkt
180 PacketPtr pkt = new Packet(req, cmd); local
210 queueDma(PacketPtr pkt) argument
224 PacketPtr pkt = transmitList.front(); local
268 PacketPtr pkt = transmitList.front(); local
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/gem5/src/mem/cache/prefetch/
H A Dqueued.cc63 pkt = new Packet(req, MemCmd::HardPFReq);
64 pkt->allocate();
67 pkt->req->setPC(pfInfo.getPC());
108 delete p.pkt;
143 QueuedPrefetcher::notify(const PacketPtr &pkt, const PrefetchInfo &pfi) argument
154 delete itr->pkt;
187 insert(pkt, new_pfi, addr_prio.second);
214 PacketPtr pkt = pfq.front().pkt; local
219 assert(pkt !
341 createPrefetchRequest(Addr addr, PrefetchInfo const &pfi, PacketPtr pkt) argument
352 insert(const PacketPtr &pkt, PrefetchInfo &new_pfi, int32_t priority) argument
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H A Dbase.hh77 void notify(const PacketPtr &pkt) override;
235 * @param pkt PacketPtr used to generate the PrefetchInfo
240 PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
297 * @param pkt The memory request causing the event
300 bool observeAccess(const PacketPtr &pkt, bool miss) const;
345 virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
348 virtual void notifyFill(const PacketPtr &pkt) argument
367 * @param pkt The memory request causing the event
370 void probeNotify(const PacketPtr &pkt, bool miss);
/gem5/src/gpu-compute/
H A Dtlb_coalescer.hh106 * of the pkt from the ComputeUnit's perspective, but another
134 // account the number of all uncoalesced requests this pkt "represents"
145 void updatePhysAddresses(PacketPtr pkt);
167 virtual bool recvTimingReq(PacketPtr pkt);
168 virtual Tick recvAtomic(PacketPtr pkt) { return 0; } argument
169 virtual void recvFunctional(PacketPtr pkt);
196 virtual bool recvTimingResp(PacketPtr pkt);
197 virtual Tick recvAtomic(PacketPtr pkt) { return 0; } argument
198 virtual void recvFunctional(PacketPtr pkt);
H A Ddispatcher.hh133 virtual bool recvTimingResp(PacketPtr pkt) { return true; } argument
134 virtual Tick recvAtomic(PacketPtr pkt) { return 0; } argument
135 virtual void recvFunctional(PacketPtr pkt) { } argument
147 Tick read(PacketPtr pkt) override;
148 Tick write(PacketPtr pkt) override;
H A Dgpu_tlb.hh232 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
233 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
246 PacketPtr pkt);
248 void handleFuncTranslationReturn(PacketPtr pkt, tlbOutcome outcome);
250 void pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt,
256 void issueTLBLookup(PacketPtr pkt);
270 virtual bool recvTimingReq(PacketPtr pkt);
271 virtual Tick recvAtomic(PacketPtr pkt) { return 0; } argument
272 virtual void recvFunctional(PacketPtr pkt);
299 virtual bool recvTimingResp(PacketPtr pkt);
300 recvAtomic(PacketPtr pkt) argument
301 recvFunctional(PacketPtr pkt) argument
391 PacketPtr pkt; member in class:X86ISA::GpuTLB::TLBEvent
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/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh99 bool recvTimingResp(PacketPtr pkt);
142 bool recvTimingResp(PacketPtr pkt) argument
143 { return trafficGen.recvTimingResp(pkt); }
145 void recvTimingSnoopReq(PacketPtr pkt) { } argument
147 void recvFunctionalSnoop(PacketPtr pkt) { } argument
149 Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } argument
179 bool allocateWaitingRespSlot(PacketPtr pkt) argument
181 assert(waitingResp.find(pkt->req) == waitingResp.end());
182 assert(pkt->needsResponse());
184 waitingResp[pkt
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/gem5/src/cpu/simple/
H A Dtiming.cc75 pkt = _pkt;
259 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
264 const RequestPtr &req = pkt->req;
268 if (pkt->isRead() && pkt->req->isLLSC()) {
269 TheISA::handleLockedRead(thread, pkt->req);
272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
273 new IprEvent(pkt, this, clockEdge(delay));
276 } else if (!dcachePort.sendTimingReq(pkt)) {
278 dcache_pkt = pkt;
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H A Datomic.cc129 AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) argument
131 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
132 pkt->cmdString());
136 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
141 pkt, dcachePort.cacheBlockMask);
278 AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
280 return port.sendAtomic(pkt);
284 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
286 DPRINTF(SimpleCPU, "received snoop pkt fo
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/gem5/src/dev/net/
H A Dpktfifo.cc47 EthPacketPtr &pkt = i->packet; local
48 while (offset >= pkt->length) {
49 offset -= pkt->length;
56 unsigned size = min(pkt->length - offset, len);
57 memcpy(data, pkt->data, size);
/gem5/src/mem/qos/
H A Dq_policy.cc76 const auto& pkt = *pkt_it; local
78 panic_if(!pkt->req,
82 MasterID m_id = pkt->req->masterId();
139 LrgQueuePolicy::enqueuePacket(PacketPtr pkt) argument
141 MasterID m_id = pkt->masterId();
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.cc55 GarnetSyntheticTraffic::CpuPort::recvTimingResp(PacketPtr pkt) argument
57 tester->completeRequest(pkt);
68 GarnetSyntheticTraffic::sendPkt(PacketPtr pkt) argument
70 if (!cachePort.sendTimingReq(pkt)) {
71 retryPkt = pkt; // RubyPort will retry sending
129 GarnetSyntheticTraffic::completeRequest(PacketPtr pkt) argument
133 pkt->isWrite() ? "write" : "read\n",
134 pkt->req->getPaddr());
136 assert(pkt->isResponse());
138 delete pkt;
318 PacketPtr pkt = new Packet(req, requestType); local
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/gem5/src/dev/x86/
H A Di82094aa.cc89 X86ISA::I82094AA::recvResponse(PacketPtr pkt) argument
92 delete pkt;
97 X86ISA::I82094AA::read(PacketPtr pkt) argument
99 assert(pkt->getSize() == 4);
100 Addr offset = pkt->getAddr() - pioAddr;
103 pkt->setLE<uint32_t>(regSel);
106 pkt->setLE<uint32_t>(readReg(regSel));
111 pkt->makeAtomicResponse();
116 X86ISA::I82094AA::write(PacketPtr pkt) argument
118 assert(pkt
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/gem5/src/dev/sparc/
H A Diob.hh120 void writeIob(PacketPtr pkt);
121 void writeJBus(PacketPtr pkt);
122 void readIob(PacketPtr pkt);
123 void readJBus(PacketPtr pkt);
135 Tick read(PacketPtr pkt) override;
136 Tick write(PacketPtr pkt) override;
/gem5/src/dev/alpha/
H A Dbackdoor.hh115 Tick read(PacketPtr pkt) override;
116 Tick write(PacketPtr pkt) override;
H A Dtsunami_io.hh126 Tick read(PacketPtr pkt) override;
127 Tick write(PacketPtr pkt) override;
H A Dtsunami_cchip.hh95 Tick read(PacketPtr pkt) override;
97 Tick write(PacketPtr pkt) override;

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