cpu/simple/timing.cc

75     pkt = _pkt;
259 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
264     const RequestPtr &req = pkt->req;
268     if (pkt->isRead() && pkt->req->isLLSC()) {
269         TheISA::handleLockedRead(thread, pkt->req);
272         Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
273         new IprEvent(pkt, this, clockEdge(delay));
276     } else if (!dcachePort.sendTimingReq(pkt)) {
278         dcache_pkt = pkt;
294     PacketPtr pkt = buildPacket(req, read);
295     pkt->dataDynamic<uint8_t>(data);
299         pkt->makeResponse();
300         completeDataAccess(pkt);
302         handleReadPacket(pkt);
314             dcache_pkt = pkt;
316             threadSnoop(pkt, curThread);
319             completeDataAccess(pkt);
403     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
405     pkt->dataDynamic<uint8_t>(data);
410     pkt->senderState = main_send_state;
414     pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
415     pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
614 TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
618             if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
621             TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
705         DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
774 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
778     DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
779             pkt->getAddr() : 0);
783     assert(!pkt || !pkt->isError());
791     if (pkt)
792         pkt->req->setAccessLatency();
839     if (pkt) {
840         delete pkt;
847     cpu->completeIfetch(pkt);
851 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
853     DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
858     tickEvent.schedule(pkt, cpu->clockEdge());
878 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
882     assert(!pkt->isError());
884            pkt->req->getFlags().isSet(Request::NO_ACCESS));
886     pkt->req->setAccessLatency();
891     if (pkt->senderState) {
893             dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
895         delete pkt;
911             pkt = big_pkt;
917     Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
929     delete pkt;
947 TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
950         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
959     if (pkt->isInvalidate() || pkt->isWrite()) {
961             TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
967 TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
970         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
977 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
979     DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
985         tickEvent.schedule(pkt, cpu->clockEdge());
1000     cpu->completeDataAccess(pkt);
1049     : pkt(_pkt), cpu(_cpu)
1057     cpu->completeDataAccess(pkt);