Searched refs:packet (Results 51 - 59 of 59) sorted by relevance
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/gem5/src/dev/net/ |
H A D | i8254xGBe.hh | 70 // packet fifos 85 // Number of bytes copied from current RX packet 258 /** The packet that is currently being dmad to memory if any */ 357 /** Bytes of packet that have been copied, so we know when to 364 /** Write the given packet into the buffer(s) pointed to by the 367 * @param packet ethernet packet to write 368 * @param pkt_offset bytes already copied from the packet to memory 371 int writePacket(EthPacketPtr packet, int pkt_offset); 373 /** Called by event when dma to write packet i [all...] |
H A D | ns_gige.cc | 49 #include "mem/packet.hh" 1157 * the packet as it arrives, and not have to wait for the 1158 * full packet ot be in the receive fifo. 1163 DPRINTF(EthernetSM, "****processing receive of new packet****\n"); 1165 // If we don't have a packet, grab a new one from the fifo. 1211 //if (rxPktBytes == 0) { /* packet is done */ 1213 DPRINTF(EthernetSM, "done with receiving packet\n"); 1573 DPRINTF(EthernetSM, "****starting the tx of a new packet****\n"); 1600 } else { /* this packet is totally done */ 1601 DPRINTF(EthernetSM, "This packet i 1911 rxFilter(const EthPacketPtr &packet) argument 1954 recvPacket(EthPacketPtr packet) argument [all...] |
/gem5/src/cpu/minor/ |
H A D | lsq.hh | 131 /** Load/store indication used for building packet. This isn't 141 * request needs to have its packet updated as this 143 PacketPtr packet; member in class:Minor::LSQ::LSQRequest 205 /** Make a packet to use with the memory transaction */ 229 /** Get the next packet to issue for this request. For split 235 /** Step to the next packet for the next call to getHeadPacket */ 245 /** Retire a response packet into the LSQRequest packet possibly 290 /** Get the head packet as counted by numIssuedFragments */ 303 /** Keep the given packet a [all...] |
/gem5/configs/common/ |
H A D | HMC.py | 70 # account for the latency of packet serialization and controller latency. We 72 # to receive the whole packet to start the serialization. But the 73 # deserializer waits for the complete packet to check its integrity first. 152 # Latency to forward a packet via the interconnect [1](two levels of FIFOs 205 controller to process the packet") 210 help="The latency experienced by every packet\ 211 regardless of size of packet")
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/gem5/src/gpu-compute/ |
H A D | compute_unit.cc | 630 // Is the packet returned a Kernel End or Barrier 829 // fields in the request will be populated, but not in the packet. 830 // here we create the new packet so we can set the size, addr, 866 // No more packet will be issued till 897 // the addr of the packet is not modified, so we need to create a new 898 // packet, or otherwise the memory access will have the old virtual 899 // address sent in the translation packet, instead of the physical 904 // Translation is done. It is safe to send the packet to memory. 964 // create packet 967 // set packet' [all...] |
/gem5/src/cpu/o3/ |
H A D | lsq.hh | 91 /** The main packet from a split load, used during writeback. */ 93 /** A second packet from a split store that needs sending. */ 103 /** Whether or not there is a packet that needs sending. */ 112 /** Completes a packet and returns whether the access is finished. */ 196 * | | Send packet |<------+ 425 * The LSQRequest owns the request. If the packet has already been 486 PacketPtr packet(int idx = 0) { return _packets.at(idx); } function 492 return packet(); 562 /** Update the status to reflect that a packet was sent. */ 568 /** Update the status to reflect that a packet wa [all...] |
H A D | lsq_unit_impl.hh | 60 #include "mem/packet.hh" 806 PacketPtr new_pkt = new Packet(*req->packet());
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/gem5/src/mem/ |
H A D | dram_ctrl.cc | 272 // do the actual memory access and turn the packet into a response 403 // create the corresponding DRAM packet with the entry time and 423 // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 446 // packet we are looking at 464 // If not found in the write q, make a DRAM packet and 487 // log packet 552 // log packet 596 for (const auto& packet : queue) { 597 DPRINTF(DRAM, "Read %lu\n", packet->addr); 602 for (const auto& packet [all...] |
/gem5/src/mem/cache/ |
H A D | base.cc | 232 // queue the packet for deletion, as the sending cache is 358 // of the bus, if the packet comes from it. 363 // Here we reset the timing of the packet. 368 // the packet in a response 411 "%s saw a non-zero packet delay\n", name()); 563 DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 697 // memory address into the packet 785 // that we send the packet straight away, so do not 789 // free the request and packet 917 // the packet a [all...] |
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