Searched refs:op1 (Results 26 - 29 of 29) sorted by relevance

12

/gem5/src/arch/arm/
H A Dutility.hh308 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, argument
315 (op1 << 14) |
H A Dmiscregs.cc1200 decodeAArch64SysReg(unsigned op0, unsigned op1, argument
1208 switch (op1) {
1326 switch (op1) {
1447 switch (op1) {
1575 switch (op1) {
1619 switch (op1) {
1649 switch (op1) {
1816 switch (op1) {
1916 switch (op1) {
1968 switch (op1) {
[all...]
H A Dfaults.cc822 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; local
826 op1 = bits(machInst, 18, 16);
832 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
H A Dmiscregs.hh988 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,

Completed in 18 milliseconds

12