Searched refs:op1 (Results 26 - 29 of 29) sorted by relevance
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/gem5/src/arch/arm/ |
H A D | utility.hh | 308 msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, argument 315 (op1 << 14) |
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H A D | miscregs.cc | 1200 decodeAArch64SysReg(unsigned op0, unsigned op1, argument 1208 switch (op1) { 1326 switch (op1) { 1447 switch (op1) { 1575 switch (op1) { 1619 switch (op1) { 1649 switch (op1) { 1816 switch (op1) { 1916 switch (op1) { 1968 switch (op1) { [all...] |
H A D | faults.cc | 822 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; local 826 op1 = bits(machInst, 18, 16); 832 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
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H A D | miscregs.hh | 988 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
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