/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ua/ |
H A D | amoswap_d.S | 26 # try again after a cache miss
|
H A D | amoswap_w.S | 26 # try again after a cache miss
|
H A D | amoxor_d.S | 26 # try again after a cache miss
|
H A D | amoxor_w.S | 26 # try again after a cache miss
|
/gem5/src/mem/cache/ |
H A D | queue_entry.hh | 116 /** Block size of the cache. */ 160 virtual bool sendPacket(BaseCache &cache) = 0;
|
H A D | write_queue_entry.cc | 51 #include "mem/cache/write_queue_entry.hh" 58 #include "mem/cache/base.hh" 142 WriteQueueEntry::sendPacket(BaseCache &cache) argument 144 return cache.sendWriteQueuePacket(this);
|
H A D | write_queue_entry.hh | 59 #include "mem/cache/queue_entry.hh" 95 bool sendPacket(BaseCache &cache) override;
|
H A D | base.hh | 49 * Declares a basic cache interface BaseCache. 66 #include "mem/cache/cache_blk.hh" 67 #include "mem/cache/compressors/base.hh" 68 #include "mem/cache/mshr_queue.hh" 69 #include "mem/cache/tags/base.hh" 70 #include "mem/cache/write_queue.hh" 71 #include "mem/cache/write_queue_entry.hh" 91 * A basic cache interface. Implements some common functions for speed. 118 * A cache master port is used for the memory-side port of the 119 * cache, an 168 BaseCache &cache; member in class:BaseCache::CacheReqPacketQueue 173 CacheReqPacketQueue(BaseCache &cache, MasterPort &port, SnoopRespPacketQueue &snoop_resp_queue, const std::string &label) argument 222 BaseCache *cache; member in class:BaseCache::MemSidePort 290 BaseCache *cache; member in class:BaseCache::CpuSidePort [all...] |
H A D | base.cc | 49 #include "mem/cache/base.hh" 58 #include "mem/cache/compressors/base.hh" 59 #include "mem/cache/mshr.hh" 60 #include "mem/cache/prefetch/base.hh" 61 #include "mem/cache/queue_entry.hh" 62 #include "mem/cache/tags/super_blk.hh" 232 // queue the packet for deletion, as the sending cache is 266 // outstanding cache maintenance requests. 312 // out of the cache block... a more aggressive 316 // block valid so that it stays in the cache, i [all...] |
H A D | mshr.cc | 51 #include "mem/cache/mshr.hh" 60 #include "mem/cache/base.hh" 339 // - the MSHR's first (and only) non-deferred target is a cache 341 // - the new target is a cache maintenance packet (this is probably 385 // locally but is buffered unissued at some downstream cache 389 // in the standard way by the cache. The only exception is 390 // that if we're an L2+ cache buffering an UpgradeReq from a 391 // higher-level cache, and the snoop is invalidating, then our 393 // since the upper-level cache no longer has a valid copy. 394 // That is, even though the upper-level cache go 653 sendPacket(BaseCache &cache) argument [all...] |
H A D | mshr.hh | 60 #include "mem/cache/queue_entry.hh" 69 * needed to handle a cache miss including a list of target requests. 140 * downstreamPending flag for the MSHR of the cache above 156 //!< target list allocate in the cache? 174 * target coming from another cache. 194 * @param blk_addr Address of the cache block 195 * @param blk_size Size of the cache block 270 * @param readTime Tick at which the packet is processed by this cache 280 * Convert upgrades to the equivalent request if the cache line they 293 * span the entire cache lin [all...] |
/gem5/configs/ruby/ |
H A D | MI_example.py | 70 # Only one cache exists for this protocol, so by default use the L1D 73 cache = L1Cache(size = options.l1d_size, 90 # Only one unified L1 cache exists. Can cache instructions and data. 91 l1_cntrl = L1Cache_Controller(version=i, cacheMemory=cache, 97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
|
H A D | MESI_Three_Level.py | 132 cache = l1_cache, l2_select_num_bits = l2_bits,
|
/gem5/src/mem/ruby/system/ |
H A D | WeightedLRUPolicy.cc | 39 : AbstractReplacementPolicy(p), m_cache(p->cache)
|
/gem5/src/mem/cache/prefetch/ |
H A D | base.hh | 109 /** Whether this event comes from a cache miss */ 190 * Check if this event comes from a cache miss 191 * @result true if this event comes from a cache miss 238 * @param miss whether this event comes from a cache miss 260 /** Pointr to the parent cache. */ 261 BaseCache* cache; member in class:BasePrefetcher 263 /** The block size of the parent cache. */ 266 /** log_2(block size of the parent cache). */ 269 /** Only consult prefetcher on cache misses? */ 298 * @param miss whether this event comes from a cache mis [all...] |
H A D | queued.cc | 40 #include "mem/cache/prefetch/queued.hh" 48 #include "mem/cache/base.hh" 241 .desc("number of redundant prefetches already in cache/mshr dropped"); 290 "cache/MSHR prefetch addr:%#x\n", target_paddr); 426 "cache/MSHR prefetch addr:%#x\n", target_paddr); 442 dpp.tc = cache->system->getThreadContext(translation_req->contextId());
|
/gem5/ext/testlib/ |
H A D | helper.py | 111 multiple times on a cache miss. 130 Make a cache key from optionally typed positional and keyword arguments. 133 argument and its data type is known to cache its hash value, then that 161 sentinel = object() # unique object used to signal cache misses 163 cache = {} 167 result = cache.get(key, sentinel) 171 cache[key] = result
|
/gem5/ext/mcpat/cacti/ |
H A D | cacti_interface.h | 363 int cache, 420 int cache, //scratch ram or cache
|
H A D | io.cc | 52 /* Parses "cache.cfg" file */ 144 if (!strncmp("-cache type", line, strlen("-cache type"))) { 145 sscanf(line, "-cache type%[^\"]\"%[^\"]\"", jk, temp_var); 147 if (!strncmp("cache", temp_var, sizeof("cache"))) { 183 * later based on the cache size, bank count, and associativity 323 if (!strncmp("-Cache model", line, strlen("-cache model"))) { 454 if (!strncmp("-Force cache config", line, strlen("-Force cache confi 671 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int banks, double tech_node, int page_sz, int burst_length, int pre_width, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_area, int obj_func_cycle_time, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int is_nuca, int core_count, int cache_level, int nuca_bank_count, int nuca_obj_func_delay, int nuca_obj_func_dynamic_power, int nuca_obj_func_leakage_power, int nuca_obj_func_area, int nuca_obj_func_cycle_time, int nuca_dev_func_delay, int nuca_dev_func_dynamic_power, int nuca_dev_func_leakage_power, int nuca_dev_func_area, int nuca_dev_func_cycle_time, int REPEATERS_IN_HTREE_SEGMENTS_in, int p_input) argument 861 cacti_interface( int cache_size, int line_size, int associativity, int rw_ports, int excl_read_ports, int excl_write_ports, int single_ended_read_ports, int search_ports, int banks, double tech_node, int output_width, int specific_tag, int tag_width, int access_mode, int cache, int main_mem, int obj_func_delay, int obj_func_dynamic_power, int obj_func_leakage_power, int obj_func_cycle_time, int obj_func_area, int dev_func_delay, int dev_func_dynamic_power, int dev_func_leakage_power, int dev_func_area, int dev_func_cycle_time, int ed_ed2_none, int temp, int wt, int data_arr_ram_cell_tech_flavor_in, int data_arr_peri_global_tech_flavor_in, int tag_arr_ram_cell_tech_flavor_in, int tag_arr_peri_global_tech_flavor_in, int interconnect_projection_type_in, int wire_inside_mat_type_in, int wire_outside_mat_type_in, int REPEATERS_IN_HTREE_SEGMENTS_in, int VERTICAL_HTREE_WIRES_OVER_THE_ARRAY_in, int BROADCAST_ADDR_DATAIN_OVER_VERTICAL_HTREES_in, int PAGE_SIZE_BITS_in, int BURST_LENGTH_in, int INTERNAL_PREFETCH_WIDTH_in, int force_wiretype, int wiretype, int force_config, int ndwl, int ndbl, int nspd, int ndcm, int ndsam1, int ndsam2, int ecc) argument [all...] |
/gem5/configs/common/ |
H A D | HMC.py | 289 cache line size will be set to this value.\nDefault:\
|
/gem5/ext/pybind11/include/pybind11/ |
H A D | pytypes.h | 513 if (!cache) { cache = Policy::get(obj, key); } 514 return cache; 520 mutable object cache; member in class:accessor
|
H A D | pybind11.h | 1647 // New cache entry created; set up a weak reference to automatically remove it if the type 2033 auto &cache = detail::get_internals().inactive_overload_cache; local 2034 if (cache.find(key) != cache.end()) 2039 cache.insert(key);
|