Searched refs:bus (Results 26 - 30 of 30) sorted by relevance

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/gem5/src/dev/mips/
H A Dmalta.hh111 calcPciConfigAddr(int bus, int dev, int func) argument
/gem5/src/dev/sparc/
H A Dt1000.cc85 T1000::calcPciConfigAddr(int bus, int dev, int func) argument
/gem5/src/dev/arm/
H A DSMMUv3.py188 def connect(self, device, bus):
196 self.master = bus.slave
197 self.control = bus.master
/gem5/configs/example/arm/
H A Ddevices.py161 def connectMemSide(self, bus):
162 bus.slave
164 self.l2.mem_side = bus.slave
167 cpu.connectAllPorts(bus)
/gem5/src/cpu/
H A DBaseCPU.py229 def connectCachedPorts(self, bus):
231 exec('self.%s = bus.slave' % p)
233 def connectUncachedPorts(self, bus):
235 exec('self.%s = bus.master' % p)
237 exec('self.%s = bus.slave' % p)

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