Searched refs:True (Results 76 - 100 of 290) sorted by relevance

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/gem5/configs/ruby/
H A DGPU_RfO.py123 self.sequencer.is_cpu_sequencer = True
131 self.sequencer1.is_cpu_sequencer = True
179 self.sequencer.is_cpu_sequencer = True
208 self.sequencer.is_cpu_sequencer = True
210 self.use_seq_not_coal = True
275 resourceStalls = True
414 default=True)
487 dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
502 dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
503 dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True)
[all...]
H A DMI_example.py109 l1_cntrl.requestFromCache = MessageBuffer(ordered = True)
111 l1_cntrl.responseFromCache = MessageBuffer(ordered = True)
113 l1_cntrl.forwardToCache = MessageBuffer(ordered = True)
115 l1_cntrl.responseToCache = MessageBuffer(ordered = True)
136 dir_cntrl.requestToDir = MessageBuffer(ordered = True)
138 dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
143 dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
170 dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
188 io_controller.responseFromDir = MessageBuffer(ordered = True)
/gem5/src/mem/slicc/ast/
H A DIsValidPtrExprAST.py45 var_type, var_code = self.variable.inline(True);
H A DReturnStatementAST.py40 actual_type, ecode = self.expr_ast.inline(True)
/gem5/src/mem/slicc/generate/
H A Dhtml.py41 mode_is_normal = True
/gem5/util/
H A Dhgfilesize.py32 return True # This is invalid
H A Dcscope-index.py45 return True
H A Dcompile167 bool_option("syscall", default=True,
169 bool_option("fullsys", default=True,
180 options.all_bin = True
181 options.prof = True
182 options.all_isa = True
185 options.debug = True
186 options.opt = True
187 options.fast = True
203 options.alpha = True
204 options.mips = True
[all...]
/gem5/ext/pybind11/pybind11/
H A D__main__.py14 get_include(True)]
/gem5/tests/gem5/test_build/
H A Dtest_build.py52 function = TestFunction(lambda fixtures: True, name,
/gem5/configs/common/
H A DSimpleOpts.py67 called_parse_args = True
/gem5/configs/example/
H A Druby_random_test.py93 check_flush = True
126 system.ruby.randomization = True
140 ruby_port.no_retry_on_stall = True
146 ruby_port.using_ruby_tester = True
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py153 """True if the CPU model or ISA requires sending evictions from caches
161 return True
176 self.requestToDir = MessageBuffer(ordered = True)
178 self.responseToDirOrSibling = MessageBuffer(ordered = True)
180 self.forwardFromDir = MessageBuffer(ordered = True)
182 self.responseFromDirOrSibling = MessageBuffer(ordered = True)
208 self.requestFromCache = MessageBuffer(ordered = True)
210 self.responseFromCache = MessageBuffer(ordered = True)
213 self.responseToCache = MessageBuffer(ordered = True)
215 self.forwardToCache = MessageBuffer(ordered = True)
[all...]
H A Druby_caches_MI_example.py150 """True if the CPU model or ISA requires sending evictions from caches
158 return True
165 self.requestFromCache = MessageBuffer(ordered = True)
167 self.responseFromCache = MessageBuffer(ordered = True)
169 self.forwardToCache = MessageBuffer(ordered = True)
171 self.responseToCache = MessageBuffer(ordered = True)
197 self.requestToDir = MessageBuffer(ordered = True)
199 self.dmaRequestToDir = MessageBuffer(ordered = True)
204 self.dmaResponseFromDir = MessageBuffer(ordered = True)
/gem5/src/cpu/simple/
H A DAtomicSimpleCPU.py59 return True
/gem5/src/dev/virtio/
H A DVirtIO.py50 abstract = True
/gem5/src/dev/serial/
H A DUart.py49 abstract = True
/gem5/src/mem/qos/
H A DQoSMemCtrl.py49 abstract = True
/gem5/src/mem/ruby/network/
H A DNetwork.py38 abstract = True
/gem5/util/systemc/systemc_within_gem5/systemc_sc_main/
H A Dconfig.py40 root = Root(full_system=True, systemc_kernel=kernel)
/gem5/src/mem/ruby/slicc_interface/
H A DController.py50 abstract = True
/gem5/src/dev/
H A DIntPin.py39 INT_SOURCE_ROLE, desc, is_source=True)
/gem5/src/arch/x86/insts/
H A Dmicroop.hh50 True, enumerator in enum:X86ISA::ConditionTests::CondTest
51 NotFalse = True,
/gem5/configs/dist/
H A Dsw.py58 is_switch = True,
75 root = Root(full_system = True, system = system)
/gem5/src/arch/arm/
H A DArmTLB.py74 is_stage2 = True
79 is_stage2 = True

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