1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28#          Brad Beckmann
29
30from m5.params import *
31from m5.objects.ClockedObject import ClockedObject
32from m5.objects.BasicLink import BasicLink
33
34class RubyNetwork(ClockedObject):
35    type = 'RubyNetwork'
36    cxx_class = 'Network'
37    cxx_header = "mem/ruby/network/Network.hh"
38    abstract = True
39    topology = Param.String("Not Specified",
40                            "the name of the imported topology module")
41
42    number_of_virtual_networks = Param.Unsigned("Number of virtual networks "
43           "used by the coherence protocol in use.  The on-chip network "
44           "assumes the protocol numbers vnets starting from 0.  Therefore, "
45           "the number of virtual networks should be one more than the "
46           "highest numbered vnet in use.")
47    control_msg_size = Param.Int(8, "")
48    ruby_system = Param.RubySystem("")
49
50    routers = VectorParam.BasicRouter("Network routers")
51    netifs = VectorParam.ClockedObject("Network Interfaces")
52    ext_links = VectorParam.BasicExtLink("Links to external nodes")
53    int_links = VectorParam.BasicIntLink("Links between internal nodes")
54
55    slave = VectorSlavePort("CPU slave port")
56    master = VectorMasterPort("CPU master port")
57