Searched refs:TheISA (Results 76 - 100 of 125) sorted by relevance

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/gem5/src/cpu/o3/
H A Dfetch_impl.hh124 instSize = sizeof(TheISA::MachInst);
145 decoder[tid] = new TheISA::Decoder(params->isa[tid]);
559 const DynInstPtr &inst, TheISA::PCState &nextPC)
567 TheISA::advancePC(nextPC, inst->staticInst);
735 TheISA::PCState fetchPC = pc[tid];
761 DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
813 DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
883 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
1105 StaticInstPtr curMacroop, TheISA::PCState thisPC,
1106 TheISA
[all...]
H A Dcommit.hh315 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
318 void pcState(const TheISA::PCState &val, ThreadID tid)
443 TheISA::PCState pc[Impl::MaxThreads];
H A Drename_map.hh173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
174 using VecReg = TheISA::VecReg;
175 using VecPredReg = TheISA::VecPredReg;
H A Dregfile.cc81 if (TheISA::NumCCRegs == 0 && _numPhysicalCCRegs != 0) {
128 for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {
H A Dlsq_unit_impl.hh382 TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask);
401 TheISA::handleLockedSnoopHit(ld_inst.get());
437 TheISA::handleLockedSnoopHit(ld_inst.get());
534 using namespace TheISA;
602 using namespace TheISA;
795 bool success = TheISA::handleLockedWrite(inst.get(),
/gem5/src/sim/
H A Dsystem.hh288 Arch getArch() const { return Arch::TheISA; }
293 Addr getPageBytes() const { return TheISA::PageBytes; }
298 Addr getPageShift() const { return TheISA::PageShift; }
H A Dprocess.cc76 using namespace TheISA;
342 stack_min -= TheISA::PageBytes;
345 allocateMem(stack_min, TheISA::PageBytes);
464 Addr interp_mapsize = roundUp(interp->mapSize(), TheISA::PageBytes);
/gem5/src/cpu/
H A Dreg_class.hh85 static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
143 return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
145 regIdx == TheISA::ZeroReg));
/gem5/src/gpu-compute/
H A Dcompute_unit.cc800 TheISA::GpuTLB::TranslationState *translation_state =
801 new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false,
892 pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode,
912 TheISA::GpuTLB::TranslationState *sender_state =
913 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1080 TheISA::GpuTLB::TranslationState *translation_state =
1081 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
1153 int stride = last ? (roundDown(vaddr, TheISA::PageBytes) -
1154 roundDown(last, TheISA::PageBytes)) >> TheISA
[all...]
H A Dshader.hh66 namespace TheISA namespace
H A Dgpu_tlb.cc95 * TheISA::PageBytes), then there are various issues w/ the current
165 int set = (vpn >> TheISA::PageShift) & setMask;
185 int set = (va >> TheISA::PageShift) & setMask;
215 int set = (va >> TheISA::PageShift) & setMask;
267 int set = (va >> TheISA::PageShift) & setMask;
1039 TheISA::PageBytes);
1438 Addr virt_page_addr = roundDown(vaddr, TheISA::PageBytes);
1489 TheISA::PageBytes);
1618 TheISA::PageBytes);
/gem5/src/cpu/checker/
H A Dcpu.hh90 typedef TheISA::MachInst MachInst;
91 using VecRegContainer = TheISA::VecRegContainer;
441 TheISA::PCState pcState() const override { return thread->pcState(); }
443 pcState(const TheISA::PCState &val) override
503 recordPCChange(const TheISA::PCState &val)
607 TheISA::PCState newPCState;
H A Dcpu_impl.hh68 using namespace TheISA;
82 TheISA::PCState pcState = thread->pcState();
83 TheISA::advancePC(pcState, curStaticInst);
295 TheISA::PCState pcState = thread->pcState();
319 fetchOffset += sizeof(TheISA::MachInst);
/gem5/src/dev/x86/
H A Dpc.cc52 using namespace TheISA;
/gem5/src/mem/
H A Dse_translating_port_proxy.cc56 using namespace TheISA;
/gem5/src/cpu/pred/
H A Dsimple_indirect.cc92 SimpleIndirectPredictor::lookup(Addr br_addr, TheISA::PCState& target,
176 InstSeqNum seq_num, void * indirect_history, const TheISA::PCState& target,
/gem5/src/cpu/simple/
H A Dtiming.cc64 using namespace TheISA;
269 TheISA::handleLockedRead(thread, pkt->req);
272 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
307 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
482 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
621 TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
673 TheISA::PCState pcState = thread->pcState();
961 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
H A Dexec_context.hh63 using VecRegContainer = TheISA::VecRegContainer;
64 using VecElem = TheISA::VecElem;
77 TheISA::PCState predPC;
/gem5/src/cpu/minor/
H A Dfetch1.cc94 if ((lineSnap % sizeof(TheISA::MachInst)) != 0) {
96 "of sizeof(TheISA::MachInst) (%d)\n", name_,
97 sizeof(TheISA::MachInst));
101 (maxLineWidth % sizeof(TheISA::MachInst)) == 0))
104 " sizeof(TheISA::MachInst)"
106 name_, sizeof(TheISA::MachInst), lineSnap);
202 ((Addr) (1 << sizeof(TheISA::MachInst)) - 1);
H A Dlsq.cc81 TheISA::PCState old_pc = thread.pcState();
103 TheISA::PCState old_pc = thread.pcState();
1122 TheISA::PCState old_pc = thread.pcState();
1127 TheISA::handleLockedRead(&context, request->request);
1129 do_access = TheISA::handleLockedWrite(&context,
1188 TheISA::handleIprRead(thread, packet);
1191 TheISA::handleIprWrite(thread, packet);
1758 TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,
1780 TheISA::handleLockedSnoop(cpu.getContext(tid), pkt,
H A Dexecute.hh224 MinorDynInstPtr inst, const TheISA::PCState &target,
H A Dfunc_unit.cc207 TheISA::ExtMachInst mach_inst = inst->machInst;
H A Ddyn_inst.cc150 os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
H A Dexecute.cc219 const TheISA::PCState &pc_before = inst->pc;
220 TheISA::PCState target = thread->pcState();
244 TheISA::advancePC(target, inst->staticInst);
298 MinorDynInstPtr inst, const TheISA::PCState &target,
462 TheISA::PCState old_pc = thread->pcState();
1005 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState();
1478 MinorDynInst::bubble(), TheISA::PCState(0), branch);
/gem5/src/dev/virtio/
H A Dbase.hh71 return TheISA::gtoh(v);
77 return TheISA::htog(v);

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