Searched refs:SimObject (Results 326 - 350 of 357) sorted by relevance

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/gem5/src/python/m5/stats/
H A D__init__.py259 if m5.SimObject.isSimObjectVector(obj):
/gem5/configs/example/
H A Dread_config.py67 if inspect.isclass(cls) and issubclass(cls, m5.objects.SimObject) }
177 """Find and configure (with just non-SimObject parameters)
189 raise Exception('No SimObject type %s is available to'
225 if issubclass(param.ptype, m5.objects.SimObject):
361 # populating not-SimObject-valued parameters
368 # Now fill in SimObject-valued parameters in the knowledge that
392 """Get a list of all the SimObject paths in the configuration"""
396 """Get a single param or SimObject reference from the configuration
401 """Get a vector param or vector of SimObject references from the
501 element which is a full SimObject descriptio
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/gem5/src/python/m5/
H A Dparams.py79 from . import SimObject
80 return SimObject.isSimObject(*args, **kwargs)
83 from . import SimObject
84 return SimObject.isSimObjectSequence(*args, **kwargs)
87 from . import SimObject
88 return SimObject.isSimObjectClass(*args, **kwargs)
100 # Dummy base class to identify types that are legitimate for SimObject
184 from . import SimObject
185 ptype = SimObject.allClasses[self.ptype_str]
211 # deferred evaluation of SimObject; continu
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/gem5/src/arch/arm/
H A Dpmu.cc60 : SimObject(p), BaseISADevice(),
129 PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
H A Disa.hh66 class ISA : public SimObject
752 using SimObject::startup;
H A Dtlb.hh224 void setTestInterface(SimObject *ti);
/gem5/src/mem/cache/
H A Dbase.hh1277 class WriteAllocator : public SimObject {
1280 SimObject(p),
/gem5/src/mem/ruby/structures/
H A DCacheMemory.cc59 : SimObject(p),
493 SimObject::regStats();
/gem5/src/cpu/kvm/
H A Dvm.cc295 : SimObject(params),
/gem5/src/arch/x86/
H A Disa.cc116 : SimObject(p)
/gem5/src/dev/virtio/
H A Dbase.hh570 class VirtIODeviceBase : public SimObject
598 * @name SimObject Interfaces
H A Dbase.cc327 : SimObject(params),
/gem5/src/cpu/
H A DBaseCPU.py49 from m5.SimObject import *
/gem5/src/cpu/pred/
H A Dloop_predictor.cc44 : SimObject(p), logSizeLoopPred(p->logSizeLoopPred),
H A Dstatistical_corrector.cc48 : SimObject(p),
/gem5/src/mem/
H A Dsnoop_filter.cc393 SimObject::regStats();
/gem5/src/mem/ruby/network/
H A DMessageBuffer.cc44 : SimObject(p), m_stall_map_size(0),
/gem5/src/python/m5/util/
H A Ddot_writer.py51 # with the top-most SimObject (namely root but not necessarily), the
64 from m5.SimObject import isRoot, isSimObjectVector
/gem5/src/dev/arm/
H A DRealView.py263 class RealViewTemperatureSensor(SimObject):
307 if issubclass(type(obj), SimObject):
339 if isinstance(obj, SimObject):
H A Dufs_device.hh537 class UFSSCSIDevice: SimObject
H A Dgeneric_timer.cc95 SimObject &parent,
/gem5/src/dev/storage/
H A Dide_disk.cc70 : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay),
400 SimObject::regStats();
/gem5/src/gpu-compute/
H A Dwavefront.cc52 : SimObject(p), callArgMem(nullptr), _gpuISA()
97 SimObject::regStats();
/gem5/src/base/
H A Dcp_annotate.hh144 class CPA : SimObject
/gem5/src/arch/sparc/
H A Disa.cc64 : SimObject(p)

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