Searched refs:SimObject (Results 326 - 350 of 357) sorted by relevance
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/gem5/src/python/m5/stats/ |
H A D | __init__.py | 259 if m5.SimObject.isSimObjectVector(obj):
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/gem5/configs/example/ |
H A D | read_config.py | 67 if inspect.isclass(cls) and issubclass(cls, m5.objects.SimObject) } 177 """Find and configure (with just non-SimObject parameters) 189 raise Exception('No SimObject type %s is available to' 225 if issubclass(param.ptype, m5.objects.SimObject): 361 # populating not-SimObject-valued parameters 368 # Now fill in SimObject-valued parameters in the knowledge that 392 """Get a list of all the SimObject paths in the configuration""" 396 """Get a single param or SimObject reference from the configuration 401 """Get a vector param or vector of SimObject references from the 501 element which is a full SimObject descriptio [all...] |
/gem5/src/python/m5/ |
H A D | params.py | 79 from . import SimObject 80 return SimObject.isSimObject(*args, **kwargs) 83 from . import SimObject 84 return SimObject.isSimObjectSequence(*args, **kwargs) 87 from . import SimObject 88 return SimObject.isSimObjectClass(*args, **kwargs) 100 # Dummy base class to identify types that are legitimate for SimObject 184 from . import SimObject 185 ptype = SimObject.allClasses[self.ptype_str] 211 # deferred evaluation of SimObject; continu [all...] |
/gem5/src/arch/arm/ |
H A D | pmu.cc | 60 : SimObject(p), BaseISADevice(), 129 PMU::addEventProbe(unsigned int id, SimObject *obj, const char *probe_name)
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H A D | isa.hh | 66 class ISA : public SimObject 752 using SimObject::startup;
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H A D | tlb.hh | 224 void setTestInterface(SimObject *ti);
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/gem5/src/mem/cache/ |
H A D | base.hh | 1277 class WriteAllocator : public SimObject { 1280 SimObject(p),
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/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.cc | 59 : SimObject(p), 493 SimObject::regStats();
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/gem5/src/cpu/kvm/ |
H A D | vm.cc | 295 : SimObject(params),
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/gem5/src/arch/x86/ |
H A D | isa.cc | 116 : SimObject(p)
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/gem5/src/dev/virtio/ |
H A D | base.hh | 570 class VirtIODeviceBase : public SimObject 598 * @name SimObject Interfaces
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H A D | base.cc | 327 : SimObject(params),
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 49 from m5.SimObject import *
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/gem5/src/cpu/pred/ |
H A D | loop_predictor.cc | 44 : SimObject(p), logSizeLoopPred(p->logSizeLoopPred),
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H A D | statistical_corrector.cc | 48 : SimObject(p),
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/gem5/src/mem/ |
H A D | snoop_filter.cc | 393 SimObject::regStats();
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/gem5/src/mem/ruby/network/ |
H A D | MessageBuffer.cc | 44 : SimObject(p), m_stall_map_size(0),
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/gem5/src/python/m5/util/ |
H A D | dot_writer.py | 51 # with the top-most SimObject (namely root but not necessarily), the 64 from m5.SimObject import isRoot, isSimObjectVector
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/gem5/src/dev/arm/ |
H A D | RealView.py | 263 class RealViewTemperatureSensor(SimObject): 307 if issubclass(type(obj), SimObject): 339 if isinstance(obj, SimObject):
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H A D | ufs_device.hh | 537 class UFSSCSIDevice: SimObject
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H A D | generic_timer.cc | 95 SimObject &parent,
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/gem5/src/dev/storage/ |
H A D | ide_disk.cc | 70 : SimObject(p), ctrl(NULL), image(p->image), diskDelay(p->delay), 400 SimObject::regStats();
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/gem5/src/gpu-compute/ |
H A D | wavefront.cc | 52 : SimObject(p), callArgMem(nullptr), _gpuISA() 97 SimObject::regStats();
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/gem5/src/base/ |
H A D | cp_annotate.hh | 144 class CPA : SimObject
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/gem5/src/arch/sparc/ |
H A D | isa.cc | 64 : SimObject(p)
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