Searched refs:SimObject (Results 226 - 250 of 357) sorted by relevance

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/gem5/src/learning_gem5/part2/
H A Dsimple_memobj.cc36 SimObject(params),
49 // This is the name from the Python SimObject declaration (SimpleMemobj.py)
58 return SimObject::getPort(if_name, idx);
H A Dgoodbye_object.cc37 SimObject(params), event([this]{ processEvent(); }, name() + ".event"),
H A Dsimple_memobj.hh44 class SimpleMemobj : public SimObject
/gem5/src/arch/x86/bios/
H A Dintelmp.hh88 class FloatingPointer : public SimObject
117 class BaseConfigEntry : public SimObject
131 class ExtConfigEntry : public SimObject
146 class ConfigTable : public SimObject
/gem5/src/mem/ruby/structures/
H A DWireBuffer.hh56 class WireBuffer : public SimObject
/gem5/src/cpu/o3/
H A Dfu_pool.hh71 class FUPool : public SimObject
/gem5/src/base/vnc/
H A Dvncinput.cc58 : SimObject(p), keyboard(NULL), mouse(NULL),
/gem5/src/dev/net/
H A Detherdump.cc48 : SimObject(p), stream(simout.create(p->file, true)->stream()),
H A Detherbus.cc54 : SimObject(p), ticksPerByte(p->speed), loopback(p->loopback),
H A Ddist_etherlink.cc74 : SimObject(p), linkDelay(p->delay)
116 return SimObject::getPort(if_name, idx);
/gem5/src/dev/ps2/
H A Ddevice.cc52 : SimObject(p)
/gem5/src/mem/cache/tags/indexing_policies/
H A Dbase.cc59 : SimObject(p), assoc(p->assoc),
/gem5/src/arch/arm/
H A Dstage2_mmu.hh52 class Stage2MMU : public SimObject
/gem5/src/dev/storage/
H A Dsimple_disk.cc56 : SimObject(p), system(p->system), image(p->disk)
/gem5/src/mem/cache/prefetch/
H A Dpif.hh184 * Add a SimObject and a probe name to monitor the retired instructions
185 * @param obj The SimObject pointer to listen from
188 void addEventProbeRetiredInsts(SimObject *obj, const char *name);
/gem5/src/dev/arm/
H A DGic.py41 from m5.SimObject import SimObject
75 class ArmInterruptPin(SimObject):
120 class Gicv2mFrame(SimObject):
H A Drv_ctrl.hh230 : public SimObject, RealViewCtrl::Device
234 : SimObject(p),
/gem5/src/cpu/pred/
H A DBranchPredictor.py30 from m5.SimObject import SimObject
34 class IndirectPredictor(SimObject):
57 class BranchPredictor(SimObject):
105 class TAGEBase(SimObject):
164 class LoopPredictor(SimObject):
325 class StatisticalCorrector(SimObject):
/gem5/src/sim/
H A Dsystem.cc92 : SimObject(p), _systemPort("system_port", this),
447 SimObject::regStats();
509 System::lookupMasterId(const SimObject* obj) const
513 // number of occurrences of the SimObject pointer
525 "Cannot lookup MasterID by SimObject pointer: "
526 "More than one master is sharing the same SimObject\n");
552 System::getMasterId(const SimObject* master, std::string submaster)
559 System::_getMasterId(const SimObject* master, const std::string& master_name)
589 System::leafMasterName(const SimObject* master, const std::string& submaster)
595 // the root SimObject maste
[all...]
H A Ddrain.cc76 SimObject *temp = dynamic_cast<SimObject*>(obj);
/gem5/src/arch/alpha/
H A Dinterrupts.hh49 class Interrupts : public SimObject
70 Interrupts(Params * p) : SimObject(p), cpu(NULL)
/gem5/src/cpu/minor/
H A Dfunc_unit.cc80 SimObject(params),
92 SimObject(params),
/gem5/util/systemc/gem5_within_systemc/
H A Dsc_gem5_control.cc129 SimObject *obj = manager->findObject(systemName, true);
259 SimObject *root = root_manager->findObject("root", false);
/gem5/src/arch/sparc/
H A Disa.hh50 class ISA : public SimObject
177 using SimObject::startup;
/gem5/src/dev/pci/
H A DPciDevice.py41 from m5.SimObject import SimObject

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