Searched refs:SimObject (Results 201 - 225 of 357) sorted by relevance
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | trace_gen.hh | 155 * @param obj SimObject owning this sequence generator 161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration,
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/gem5/src/dev/ps2/ |
H A D | device.hh | 54 class PS2Device : public SimObject
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/gem5/src/mem/qos/ |
H A D | policy.hh | 58 class Policy : public SimObject
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/gem5/src/mem/cache/prefetch/ |
H A D | delta_correlating_prediction_tables.hh | 50 * The main prefetcher logic is implemented on a separate SimObject as there 54 class DeltaCorrelatingPredictionTables : public SimObject
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/gem5/src/mem/ruby/network/ |
H A D | BasicLink.hh | 45 class BasicLink : public SimObject
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/gem5/src/gpu-compute/ |
H A D | GPU.py | 39 from m5.SimObject import SimObject 55 class VectorRegisterFile(SimObject): 65 class Wavefront(SimObject):
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/gem5/src/mem/cache/compressors/ |
H A D | base.hh | 54 class BaseCacheCompressor : public SimObject {
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H A D | base.cc | 76 : SimObject(p), blkSize(p->block_size) 153 SimObject::regStats();
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/gem5/src/mem/ |
H A D | external_master.hh | 67 class ExternalMaster : public SimObject
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H A D | external_slave.hh | 67 class ExternalSlave : public SimObject
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/gem5/src/mem/ruby/structures/ |
H A D | DirectoryMemory.hh | 54 class DirectoryMemory : public SimObject
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/gem5/src/arch/x86/bios/ |
H A D | smbios.hh | 65 class SMBiosStructure : public SimObject 151 class SMBiosTable : public SimObject
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/gem5/src/sim/ |
H A D | clock_domain.hh | 73 class ClockDomain : public SimObject 112 SimObject(p),
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H A D | voltage_domain.cc | 52 : SimObject(p), voltageOpPoints(p->voltage), _perfLevel(0) 133 SimObject::regStats();
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H A D | system.hh | 84 class System : public SimObject 100 SystemPort(const std::string &_name, SimObject *_owner) 257 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 351 * create a master's name by concatenating the SimObject name with the 365 * @param master SimObject related to the master 369 MasterID getMasterId(const SimObject* master, 374 * to any particular SimObject; since no SimObject is passed, 388 * Looks up the MasterID for a given SimObject 391 MasterID lookupMasterId(const SimObject* ob [all...] |
H A D | clocked_object.cc | 47 SimObject(p), Clocked(*p->clk_domain), 150 SimObject::regStats();
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/gem5/src/sim/power/ |
H A D | power_model.cc | 49 : SimObject(p), _temp(0), clocked_object(NULL) 54 : SimObject(p), states_pm(p->pm), subsystem(p->subsystem), 114 "SimObject in UNDEFINED power state! Power figures might be wrong!\n"); 141 warn("SimObject in UNDEFINED power state! "
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/gem5/src/arch/mips/ |
H A D | isa.hh | 52 class ISA : public SimObject 135 using SimObject::startup;
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/gem5/src/cpu/o3/ |
H A D | FuncUnitConfig.py | 41 from m5.SimObject import SimObject
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/gem5/src/arch/arm/ |
H A D | pmu.hh | 97 class PMU : public SimObject, public ArmISA::BaseISADevice { 102 void addEventProbe(unsigned int id, SimObject *obj, const char *name); 107 public: // SimObject and related interfaces 347 typedef std::pair<SimObject*, std::string> EventTypeEntry; 349 void addMicroarchitectureProbe(SimObject* object, 361 RegularProbe(RegularEvent *parent, SimObject* obj,
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H A D | ArmPMU.py | 41 from m5.SimObject import * 70 class ArmPMU(SimObject): 93 # Override the normal SimObject::regProbeListeners method and
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/gem5/src/dev/x86/ |
H A D | SouthBridge.py | 39 from m5.SimObject import SimObject 45 class SouthBridge(SimObject):
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/gem5/src/cpu/ |
H A D | timing_expr.hh | 90 class TimingExpr : public SimObject 94 SimObject(params)
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/gem5/src/dev/storage/ |
H A D | disk_image.hh | 51 class DiskImage : public SimObject 58 DiskImage(const Params *p) : SimObject(p), initialized(false) {}
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/gem5/src/arch/riscv/ |
H A D | interrupts.hh | 54 class Interrupts : public SimObject 70 Interrupts(Params * p) : SimObject(p), cpu(nullptr), ip(0), ie(0) {}
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