Searched refs:SimObject (Results 201 - 225 of 357) sorted by relevance

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/gem5/src/cpu/testers/traffic_gen/
H A Dtrace_gen.hh155 * @param obj SimObject owning this sequence generator
161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration,
/gem5/src/dev/ps2/
H A Ddevice.hh54 class PS2Device : public SimObject
/gem5/src/mem/qos/
H A Dpolicy.hh58 class Policy : public SimObject
/gem5/src/mem/cache/prefetch/
H A Ddelta_correlating_prediction_tables.hh50 * The main prefetcher logic is implemented on a separate SimObject as there
54 class DeltaCorrelatingPredictionTables : public SimObject
/gem5/src/mem/ruby/network/
H A DBasicLink.hh45 class BasicLink : public SimObject
/gem5/src/gpu-compute/
H A DGPU.py39 from m5.SimObject import SimObject
55 class VectorRegisterFile(SimObject):
65 class Wavefront(SimObject):
/gem5/src/mem/cache/compressors/
H A Dbase.hh54 class BaseCacheCompressor : public SimObject {
H A Dbase.cc76 : SimObject(p), blkSize(p->block_size)
153 SimObject::regStats();
/gem5/src/mem/
H A Dexternal_master.hh67 class ExternalMaster : public SimObject
H A Dexternal_slave.hh67 class ExternalSlave : public SimObject
/gem5/src/mem/ruby/structures/
H A DDirectoryMemory.hh54 class DirectoryMemory : public SimObject
/gem5/src/arch/x86/bios/
H A Dsmbios.hh65 class SMBiosStructure : public SimObject
151 class SMBiosTable : public SimObject
/gem5/src/sim/
H A Dclock_domain.hh73 class ClockDomain : public SimObject
112 SimObject(p),
H A Dvoltage_domain.cc52 : SimObject(p), voltageOpPoints(p->voltage), _perfLevel(0)
133 SimObject::regStats();
H A Dsystem.hh84 class System : public SimObject
100 SystemPort(const std::string &_name, SimObject *_owner)
257 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject,
351 * create a master's name by concatenating the SimObject name with the
365 * @param master SimObject related to the master
369 MasterID getMasterId(const SimObject* master,
374 * to any particular SimObject; since no SimObject is passed,
388 * Looks up the MasterID for a given SimObject
391 MasterID lookupMasterId(const SimObject* ob
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H A Dclocked_object.cc47 SimObject(p), Clocked(*p->clk_domain),
150 SimObject::regStats();
/gem5/src/sim/power/
H A Dpower_model.cc49 : SimObject(p), _temp(0), clocked_object(NULL)
54 : SimObject(p), states_pm(p->pm), subsystem(p->subsystem),
114 "SimObject in UNDEFINED power state! Power figures might be wrong!\n");
141 warn("SimObject in UNDEFINED power state! "
/gem5/src/arch/mips/
H A Disa.hh52 class ISA : public SimObject
135 using SimObject::startup;
/gem5/src/cpu/o3/
H A DFuncUnitConfig.py41 from m5.SimObject import SimObject
/gem5/src/arch/arm/
H A Dpmu.hh97 class PMU : public SimObject, public ArmISA::BaseISADevice {
102 void addEventProbe(unsigned int id, SimObject *obj, const char *name);
107 public: // SimObject and related interfaces
347 typedef std::pair<SimObject*, std::string> EventTypeEntry;
349 void addMicroarchitectureProbe(SimObject* object,
361 RegularProbe(RegularEvent *parent, SimObject* obj,
H A DArmPMU.py41 from m5.SimObject import *
70 class ArmPMU(SimObject):
93 # Override the normal SimObject::regProbeListeners method and
/gem5/src/dev/x86/
H A DSouthBridge.py39 from m5.SimObject import SimObject
45 class SouthBridge(SimObject):
/gem5/src/cpu/
H A Dtiming_expr.hh90 class TimingExpr : public SimObject
94 SimObject(params)
/gem5/src/dev/storage/
H A Ddisk_image.hh51 class DiskImage : public SimObject
58 DiskImage(const Params *p) : SimObject(p), initialized(false) {}
/gem5/src/arch/riscv/
H A Dinterrupts.hh54 class Interrupts : public SimObject
70 Interrupts(Params * p) : SimObject(p), cpu(nullptr), ip(0), ie(0) {}

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