Searched refs:PortID (Results 51 - 75 of 121) sorted by relevance

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/gem5/src/learning_gem5/part2/
H A Dsimple_cache.hh319 PortID idx=InvalidPortID) override;
H A Dsimple_memobj.cc45 SimpleMemobj::getPort(const std::string &if_name, PortID idx)
/gem5/src/gpu-compute/
H A Ddispatcher.hh144 PortID idx=InvalidPortID) override;
H A Dgpu_tlb.hh263 PortID _index)
290 PortID _index)
312 PortID idx=InvalidPortID) override;
H A Dcompute_unit.hh425 DataPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
437 SenderState(GPUDynInstPtr gpuDynInst, PortID _port_index,
475 SQCPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
515 DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID _index)
543 SenderState(GPUDynInstPtr gpuDynInst, PortID port_index)
605 LDSPort(const std::string &_name, ComputeUnit *_cu, PortID _id)
695 getPort(const std::string &if_name, PortID idx) override
H A Dtlb_coalescer.cc71 TLBCoalescer::getPort(const std::string &if_name, PortID idx)
74 if (idx >= static_cast<PortID>(cpuSidePort.size())) {
80 if (idx >= static_cast<PortID>(memSidePort.size())) {
/gem5/src/dev/net/
H A Ddist_etherlink.hh227 PortID idx=InvalidPortID) override;
H A Detherswitch.hh65 PortID idx=InvalidPortID) override;
H A Ddist_etherlink.cc112 DistEtherLink::getPort(const std::string &if_name, PortID idx)
/gem5/src/dev/arm/
H A Dsmmu_v3_ports.cc83 PortID _id)
/gem5/src/mem/
H A Daddr_mapper.hh67 PortID idx=InvalidPortID) override;
H A Dmem_checker_monitor.hh74 PortID idx=InvalidPortID) override;
H A Dxbar.cc80 BaseXBar::getPort(const std::string &if_name, PortID idx)
310 PortID
344 BaseXBar::recvRangeChange(PortID master_port_id)
403 PortID conflict_id = portMap.intersects(r)->second;
H A Daddr_mapper.cc57 AddrMapper::getPort(const std::string &if_name, PortID idx)
H A Dexternal_slave.cc197 ExternalSlave::getPort(const std::string &if_name, PortID idx)
H A Dmem_delay.cc64 MemDelay::getPort(const std::string &if_name, PortID idx)
H A Dsimple_mem.cc245 SimpleMemory::getPort(const std::string &if_name, PortID idx)
H A Dcomm_monitor.hh88 PortID idx=InvalidPortID) override;
/gem5/src/mem/ruby/network/
H A DNetwork.hh138 getPort(const std::string &, PortID idx=InvalidPortID) override
/gem5/src/mem/ruby/system/
H A DRubyPort.cc91 RubyPort::getPort(const std::string &if_name, PortID idx)
104 if (idx >= static_cast<PortID>(master_ports.size())) {
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
147 bool _access_backing_store, PortID id,
/gem5/src/dev/x86/
H A Di8042.hh132 getPort(const std::string &if_name, PortID idx=InvalidPortID) override
/gem5/src/dev/pci/
H A Dcopy_engine.hh197 PortID idx = InvalidPortID) override;
/gem5/src/arch/x86/
H A Dpagetable_walker.hh167 PortID idx=InvalidPortID) override;
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.hh137 PortID idx=InvalidPortID);
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh249 PortID idx=InvalidPortID) override;

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