/gem5/src/cpu/o3/probe/ |
H A D | ElasticTrace.py | 63 traceVirtAddr = Param.Bool(False, "Set to true if virtual addresses are " \
|
/gem5/src/mem/probes/ |
H A D | MemTraceProbe.py | 50 with_pc = Param.Bool(False, "Include PC info in the trace")
|
/gem5/src/python/m5/ |
H A D | __init__.py | 45 in_gem5 = False
|
/gem5/src/mem/ |
H A D | AbstractMemory.py | 53 null = Param.Bool(False, "Do not store data, always return zero")
|
H A D | MemChecker.py | 55 warn_only = Param.Bool(False, "Warn about violations only")
|
H A D | XBar.py | 86 use_default_range = Param.Bool(False, "Perform address mapping for " \ 113 point_of_coherency = Param.Bool(False, "Consider this crossbar the " \ 117 point_of_unification = Param.Bool(False, "Consider this crossbar the " \
|
/gem5/src/mem/ruby/system/ |
H A D | GPUCoalescer.py | 56 garnet_standalone = Param.Bool(False, "")
|
H A D | Sequencer.py | 47 using_ruby_tester = Param.Bool(False, "") 48 no_retry_on_stall = Param.Bool(False, "") 71 garnet_standalone = Param.Bool(False, "")
|
/gem5/src/gpu-compute/ |
H A D | GPU.py | 111 perLaneTLB = Param.Bool(False, "enable per-lane TLB") 119 xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr."); 120 debugSegFault = Param.Bool(False, "enable debugging GPU seg faults") 121 functionalTLB = Param.Bool(False, "Assume TLB causes no delay") 123 localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\ 126 countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\ 138 out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery" 150 separate_acquire_release = Param.Bool(False, 154 timing = Param.Bool(False, 'timing memory accesses') 157 translation = Param.Bool(False, "addres [all...] |
/gem5/ext/googletest/googletest/test/ |
H A D | gtest_throw_on_failure_test.py | 71 """Runs a command; returns True/False if its exit code is/isn't 0.""" 131 self.RunAndVerify(env_var_value=None, flag_value=None, should_fail=False) 138 should_fail=False) 148 should_fail=False) 158 should_fail=False) 164 should_fail=False)
|
/gem5/src/mem/cache/ |
H A D | Cache.py | 98 is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 101 prefetch_on_access = Param.Bool(False, 110 sequential_access = Param.Bool(False, 127 writeback_clean = Param.Bool(False, "Writeback clean lines") 158 writeback_clean = False
|
/gem5/src/mem/ruby/structures/ |
H A D | RubyCache.py | 44 is_icache = Param.Bool(False, "is instruction only cache"); 51 resourceStalls = Param.Bool(False, "stall if there is a resource failure")
|
/gem5/src/dev/storage/ |
H A D | DiskImage.py | 36 read_only = Param.Bool(False, "read only image")
|
/gem5/src/cpu/o3/ |
H A D | FuncUnitConfig.py | 53 OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ] 74 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 75 OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] 127 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ]
|
/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.py | 43 check_flush = Param.Bool(False, "check cache flushing")
|
/gem5/src/mem/slicc/ast/ |
H A D | LocalVariableAST.py | 34 def __init__(self, slicc, type_ast, ident, pointer = False): 47 def inline(self, get_type=False): 48 code = self.slicc.codeFormatter(fix_newlines=False)
|
/gem5/src/sim/ |
H A D | System.py | 76 mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \ 88 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when " 119 multi_thread = Param.Bool(False,
|
/gem5/util/ |
H A D | compile | 142 add_option('-n', '--no-compile', default=False, action='store_true', 144 add_option('--everything', default=False, action='store_true', 146 add_option('-E', "--experimental", action='store_true', default=False, 148 add_option('-v', "--verbose", default=False, action='store_true', 152 bool_option("debug", default=False, help="compile debug binaries") 153 bool_option("opt", default=False, help="compile opt binaries") 154 bool_option("fast", default=False, help="compile fast binaries") 155 bool_option("prof", default=False, help="compile profile binaries") 156 add_option('-a', "--all-bin", default=False, action='store_true', 160 bool_option("alpha", default=False, hel [all...] |
H A D | hgfilesize.py | 34 return False # Things are OK.
|
/gem5/src/dev/net/ |
H A D | Ethernet.py | 82 is_switch = Param.Bool(False, "true if this a link in etherswitch") 83 dist_sync_on_pseudo_op = Param.Bool(False, "Start sync with pseudo_op") 211 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 212 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 213 rss = Param.Bool(False, "Receive Side Scaling") 219 dma_data_free = Param.Bool(False, "DMA of Data is free") 220 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 260 zero_copy = Param.Bool(False, "Zero copy receive") 261 delay_copy = Param.Bool(False, "Delayed copy transmit") 262 virtual_addr = Param.Bool(False, "Virtua [all...] |
/gem5/ext/pybind11/tests/ |
H A D | test_builtin_casters.py | 257 b1 = m.refwrap_list(copy=False) 258 b2 = m.refwrap_list(copy=False) 285 assert convert(False) is False 287 assert noconvert(False) is False 291 assert convert(None) is False 313 assert convert(A(False)) is False 323 assert convert(np.bool_(False)) i [all...] |
/gem5/src/systemc/tests/tlm/endian_conv/ |
H A D | testall.py | 116 byte_enable = False, 138 if False: 186 byte_enable = False, 210 byte_enable = False, 294 if False: 312 if txn.data_width > txn.bus_width: return False 313 if txn.stream_width < txn.length: return False 314 if txn.byte_enable and len(txn.byte_enable) < txn.length: return False 319 if txn.data_width > txn.bus_width: return False 320 if txn.stream_width < txn.length: return False [all...] |
/gem5/src/dev/pci/ |
H A D | PciDevice.py | 86 BAR0LegacyIO = Param.Bool(False, "Whether BAR0 is hardwired legacy IO") 87 BAR1LegacyIO = Param.Bool(False, "Whether BAR1 is hardwired legacy IO") 88 BAR2LegacyIO = Param.Bool(False, "Whether BAR2 is hardwired legacy IO") 89 BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") 90 BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") 91 BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
|
/gem5/tests/configs/ |
H A D | rubytest-ruby.py | 65 check_flush = False 86 Ruby.create_system(options, False, system) 126 root = Root(full_system = False, system = system )
|
/gem5/src/dev/ |
H A D | Device.py | 116 ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 117 update_data = Param.Bool(False, "Update the data that is returned on writes") 119 fake_mem = Param.Bool(False,
|