Searched refs:DDR3_1600_8x8 (Results 26 - 49 of 49) sorted by relevance

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/gem5/tests/configs/
H A Dpc-switcheroo-full.py45 mem_class=DDR3_1600_8x8,
H A Drealview-switcheroo-full.py43 mem_class=DDR3_1600_8x8,
H A Drealview-switcheroo-o3.py43 mem_class=DDR3_1600_8x8,
H A Drealview-switcheroo-timing.py43 mem_class=DDR3_1600_8x8,
H A Drealview64-switcheroo-full.py44 mem_class=DDR3_1600_8x8,
H A Drealview64-switcheroo-timing.py44 mem_class=DDR3_1600_8x8,
H A Drealview64-switcheroo-o3.py44 mem_class=DDR3_1600_8x8,
H A Dtsunami-switcheroo-full.py43 mem_class=DDR3_1600_8x8,
H A Drealview64-simple-timing-dual-ruby.py43 mem_class=DDR3_1600_8x8,
H A Drealview-o3-dual.py43 mem_class=DDR3_1600_8x8,
H A Drealview-o3-checker.py43 mem_class=DDR3_1600_8x8,
H A Drealview64-o3-checker.py44 mem_class=DDR3_1600_8x8,
H A Drealview64-o3-dual.py44 mem_class=DDR3_1600_8x8,
H A Drealview64-o3.py44 mem_class=DDR3_1600_8x8,
H A Drealview-o3.py43 mem_class=DDR3_1600_8x8,
H A Dtgen-dram-ctrl.py52 system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
/gem5/configs/learning_gem5/part3/
H A Dsimple_ruby.py72 system.mem_ctrl = DDR3_1600_8x8()
/gem5/configs/learning_gem5/part1/
H A Dsimple.py82 system.mem_ctrl = DDR3_1600_8x8()
H A Dtwo_level.py137 system.mem_ctrl = DDR3_1600_8x8()
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py81 system.mem_ctrl = DDR3_1600_8x8()
H A Dsimple_memobj.py79 system.mem_ctrl = DDR3_1600_8x8()
/gem5/src/mem/
H A DDRAMCtrl.py331 class DDR3_1600_8x8(DRAMCtrl): class in inherits:DRAMCtrl
426 class HMC_2500_1x32(DDR3_1600_8x8):
508 class DDR3_2133_8x8(DDR3_1600_8x8):
/gem5/tests/gem5/cpu_tests/
H A Drun.py110 'DDR3_1600_8x8': DDR3_1600_8x8
/gem5/configs/example/
H A Dmemcheck.py222 system = System(physmem = DDR3_1600_8x8())

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