Searched hist:7868 (Results 1 - 4 of 4) sorted by relevance
| /gem5/configs/common/ | ||
| H A D | Caches.py | diff 7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. |
| H A D | CacheConfig.py | diff 7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. |
| /gem5/src/cpu/o3/ | ||
| H A D | O3CPU.py | diff 7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. |
| /gem5/src/cpu/ | ||
| H A D | BaseCPU.py | diff 7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers. Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly. |
Completed in 48 milliseconds