Searched hist:7667 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/mem/cache/ | ||
| H A D | mshr_queue.hh | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
| H A D | mshr_queue.cc | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
| H A D | mshr.hh | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
| H A D | mshr.cc | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
| H A D | cache.hh | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
| H A D | base.hh | diff 7667:aa8fd8f6a495 Thu Sep 09 14:40:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> cache: coherence protocol enhancements & bug fixes Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes. |
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