Searched hist:7599 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/cpu/ | ||
| H A D | base_dyn_inst_impl.hh | diff 7599:f6bbf266f2c8 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: mark msr/mrs instructions as SerializeBefore/After Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | misc.isa | diff 7599:f6bbf266f2c8 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: mark msr/mrs instructions as SerializeBefore/After Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR |
| /gem5/src/cpu/o3/ | ||
| H A D | inst_queue_impl.hh | diff 7599:f6bbf266f2c8 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: mark msr/mrs instructions as SerializeBefore/After Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR |
| H A D | iew_impl.hh | diff 7599:f6bbf266f2c8 Mon Aug 23 12:18:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: mark msr/mrs instructions as SerializeBefore/After Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR |
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