Searched hist:73 (Results 1 - 25 of 47) sorted by relevance
/gem5/src/arch/x86/isa/insts/general_purpose/flags/ | ||
H A D | load_and_store.py | diff 5174:73a760aa0129 Fri Oct 19 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions. |
H A D | push_and_pop.py | diff 5174:73a760aa0129 Fri Oct 19 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions. |
/gem5/src/mem/ruby/structures/ | ||
H A D | RubyPrefetcher.py | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
H A D | Prefetcher.hh | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
H A D | Prefetcher.cc | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
/gem5/src/systemc/ext/tlm_utils/ | ||
H A D | multi_passthrough_initiator_socket.h | diff 13529:73d7ab16c041 Wed Jan 09 22:04:00 EST 2019 Gabe Black <gabeblack@google.com> systemc: Fix a function which was broken during style fixes. Some brackets were misapplied while correcting the style of the TLM header files. Change-Id: I4e26d0316ca2545a5f26ad5fef0e986e42a1895b Reviewed-on: https://gem5-review.googlesource.com/c/15455 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
/gem5/src/sim/ | ||
H A D | syscall_emul_buf.hh | 10497:73a59d5e0923 Wed Oct 22 18:53:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: Put BufferArg classes in a separate header. Move the BufferArg classes that support syscall buffer args (i.e., pointers into simulated user space) out of syscall_emul.hh and into a new header syscall_emul_buf.hh so they are accessible to emulated driver implementations. Take the opportunity to add some comments as well. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | irregular_stream_buffer.cc | diff 13828:73addeac3dd3 Tue Apr 02 17:43:00 EDT 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: ISB prefetcher was triggering an assertion An assertion ignored the case when an entry of the SP table had been invalidated. Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | base.hh | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
/gem5/src/arch/x86/insts/ | ||
H A D | badmicroop.cc | diff 14277:73d5e60b3a7c Fri Sep 06 20:14:00 EDT 2019 Gabe Black <gabeblack@google.com> arch, x86: Rework the debug faults and microops. This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/arch/generic/ | ||
H A D | debugfaults.hh | diff 14277:73d5e60b3a7c Fri Sep 06 20:14:00 EDT 2019 Gabe Black <gabeblack@google.com> arch, x86: Rework the debug faults and microops. This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/mem/ruby/common/ | ||
H A D | Address.cc | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
H A D | Address.hh | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | pred.isa | diff 6741:73d89772f409 Wed Nov 11 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix some bugs in the ISA desc and fill out some instructions. |
/gem5/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/ | ||
H A D | stats.txt | diff 9247:73c3eb0dd733 Mon Sep 24 18:03:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for twosys-tsunami after setting CPU clock This patch updates the stats to reflect the addition of a clock period other than the default 1 Tick. |
/gem5/src/arch/arm/isa/ | ||
H A D | bitfields.isa | diff 6741:73d89772f409 Wed Nov 11 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix some bugs in the ISA desc and fill out some instructions. |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | debug.isa | diff 14277:73d5e60b3a7c Fri Sep 06 20:14:00 EDT 2019 Gabe Black <gabeblack@google.com> arch, x86: Rework the debug faults and microops. This makes the non-fatal microops advance the PC, and adds missing functions. The *_once Faults now also can be run once per *something*. They would previously be run once per Fault invoke function which is common to all M5WarnOnceFaults. The warn_once microop will now warn once per message. Change-Id: I05974b93f3b2700077a411b243679c2ff0e8c2cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20739 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/arch/x86/ | ||
H A D | faults.hh | diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. |
H A D | faults.cc | diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. |
H A D | pagetable_walker.hh | diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. |
H A D | tlb.hh | diff 5881:73c0aaaaf186 Mon Feb 23 03:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. |
/gem5/src/mem/ | ||
H A D | abstract_mem.hh | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
H A D | dramsim2.cc | diff 10466:73b7549d979e Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Dynamically determine page bytes in memory components This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | one_byte_opcodes.isa | diff 5174:73a760aa0129 Fri Oct 19 18:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the PUSHF, POPF, SAHF, and LAHF instructions. |
/gem5/src/arch/arm/ | ||
H A D | types.hh | diff 6741:73d89772f409 Wed Nov 11 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix some bugs in the ISA desc and fill out some instructions. |
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