Searched hist:72 (Results 26 - 39 of 39) sorted by relevance
/gem5/src/mem/cache/prefetch/ | ||
H A D | stride.cc | diff 13427:72a3afac3e78 Sun Nov 11 09:52:00 EST 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Make StridePrefetcher use Replacement Policies Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | Prefetcher.py | diff 13427:72a3afac3e78 Sun Nov 11 09:52:00 EST 2018 Daniel <odanrc@yahoo.com.br> mem-cache: Make StridePrefetcher use Replacement Policies Previously StridePrefetcher was only able to use random replacement policy. This change allows all replacement policies to be applied to the pc table. Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14360 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/cpu/o3/ | ||
H A D | rob.hh | diff 9954:72a72649a156 Thu Oct 31 14:41:00 EDT 2013 Faissal Sleiman <Faissal.Sleiman@arm.com> cpu: Construct ROB with cpu params struct instead of each variable Most other structures/stages get passed the cpu params struct. |
H A D | rob_impl.hh | diff 9954:72a72649a156 Thu Oct 31 14:41:00 EDT 2013 Faissal Sleiman <Faissal.Sleiman@arm.com> cpu: Construct ROB with cpu params struct instead of each variable Most other structures/stages get passed the cpu params struct. |
H A D | cpu.cc | diff 9954:72a72649a156 Thu Oct 31 14:41:00 EDT 2013 Faissal Sleiman <Faissal.Sleiman@arm.com> cpu: Construct ROB with cpu params struct instead of each variable Most other structures/stages get passed the cpu params struct. |
/gem5/src/cpu/pred/ | ||
H A D | BranchPredictor.py | diff 11433:72b075cdc336 Tue Apr 05 12:48:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add an indirect branch target predictor This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209 This is a re-spin of fb9d142 after the revert (bd1c6789). |
/gem5/src/arch/sparc/ | ||
H A D | faults.hh | diff 3415:72c48f292f6a Wed Oct 25 17:49:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Implemented the SPARC fill and spill handlers. src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE src/arch/sparc/process.cc: src/arch/sparc/process.hh: Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart. |
H A D | faults.cc | diff 3415:72c48f292f6a Wed Oct 25 17:49:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Implemented the SPARC fill and spill handlers. src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE src/arch/sparc/process.cc: src/arch/sparc/process.hh: Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart. |
H A D | process.cc | diff 3415:72c48f292f6a Wed Oct 25 17:49:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Implemented the SPARC fill and spill handlers. src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Added a function to do normal SPARC trap processing, and implemented the spill and fill faults for SE src/arch/sparc/process.cc: src/arch/sparc/process.hh: Added fill and spill handlers which are stuffed into the processes address space. The location of these handlers are stored in fillStart and spillStart. |
/gem5/src/systemc/core/ | ||
H A D | sc_module.cc | diff 12901:72bc9ff65802 Fri Jun 15 17:56:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add the nonstandard macro SC_NEW. This is in the Accellera implementation and in the regression tests. The implementation here is a bit different than theirs in that it uses std::unique_ptrs. Change-Id: Id3d1ad82482b94a5d99f27e02d1e447ca1944797 Reviewed-on: https://gem5-review.googlesource.com/11255 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/python/m5/ | ||
H A D | main.py | diff 7458:72af7f65f117 Tue Jun 15 02:24:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: use ipython in --interactive if it is available |
/gem5/src/sim/ | ||
H A D | system.hh | diff 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc |
H A D | system.cc | diff 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc |
H A D | syscall_emul.hh | diff 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc |
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