Searched hist:5275 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | physical.hh | diff 5275:5279ced1dd8b Mon Nov 19 18:23:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. |
| H A D | physical.cc | diff 5275:5279ced1dd8b Mon Nov 19 18:23:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. |
| /gem5/configs/common/ | ||
| H A D | Simulation.py | diff 8211:5275c2fbe957 Mon Apr 04 12:42:00 EDT 2011 Anthony Gutierrez <atgutier@umich.edu> Sim: Fix Simulation.py to allow more than 1 core for standard switching. This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1, switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are assigned only once, after switch_cpus and switch_cpus_1 are constructed. |
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