Searched hist:5149 (Results 1 - 8 of 8) sorted by relevance
| /gem5/src/arch/x86/isa/insts/system/ | ||
| H A D | __init__.py | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| H A D | msrs.py | 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| /gem5/src/arch/x86/ | ||
| H A D | x86_traits.hh | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| H A D | SConscript | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| H A D | tlb.cc | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| /gem5/src/arch/x86/isa/ | ||
| H A D | microasm.isa | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | ldstop.isa | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
| /gem5/src/arch/x86/isa/decoder/ | ||
| H A D | two_byte_opcodes.isa | diff 5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions. There are no priviledge checks, so these instructions will all work in all modes. |
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