xref: /gem5/src/arch/x86/isa/insts/system/msrs.py

# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black

microcode = '''
def macroop RDMSR
{
    ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
        dataSize=8, addressSize=8
    mov rax, rax, t2, dataSize=4
    srli t2, t2, 32, dataSize=8
    mov rdx, rdx, t2, dataSize=4
};

def macroop WRMSR
{
    .serialize_after
    mov t2, t2, rax, dataSize=4
    slli t3, rdx, 32, dataSize=8
    or t2, t2, t3, dataSize=8
    st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
        dataSize=8, addressSize=8
};

def macroop RDTSC
{
    .serialize_before
    rdtsc t1
    mov rax, rax, t1, dataSize=4
    srli rdx, t1, 32, dataSize=8
};

def macroop RDTSCP
{
    .serialize_before
    mfence
    rdtsc t1
    mov rax, rax, t1, dataSize=4
    srli rdx, t1, 32, dataSize=8
    rdval rcx, "InstRegIndex(MISCREG_TSC_AUX)", dataSize=4
};
'''