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| /gem5/src/arch/riscv/isa/ | ||
| H A D | decoder.isa | diff 12596:5102ba06fca5 Thu Mar 01 10:32:00 EST 2018 Tuan Ta <qtt2@cornell.edu> riscv: throw IllegalInstFault when decoding invalid instructions If an instruction is invalid, some assertions may in the decoder may fail the entire simulation. Instead, we want to raise an IllegalInstFault instead of failing immediately in the decoder if the invalid instruction is being speculatively executed. Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f Reviewed-on: https://gem5-review.googlesource.com/9261 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
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