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/gem5/src/dev/ | ||
H A D | mc146818.hh | diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/sim/ | ||
H A D | drain.cc | diff 11937:e6621fafa62d Tue Mar 28 09:50:00 EDT 2017 Andreas Sandberg <andreas.sandberg@arm.com> sim: Handle cases where Drainable::resume() creates objects There are cases where Drainable objects need to create new objects in Drainable::resume(). In such cases, the local drain state will be inherited from the DrainManager. We currently set the state to Running as soon as we start resuming the simulator. This means that new objects are created in the Running state rather than the Drained state, which the resume code assumes. Depending on the traversal order in DrainManager::resume(), this sometimes triggers a panic because the object being resumed is in the wrong state. This change introduces a new drain state, Resuming, that the DrainManager enters as soon as it starts resuming the simulator. Objects that are created while resuming are created in this state. Such objects are then resumed in a subsequent pass over the list of Drainable objects that need to be resumed. Once all objects have been resumed, the simulator enters the Running state. Change-Id: Ieee8645351ffbdec477e9cd2ff86fc795e459617 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com> |
H A D | core.cc | diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
H A D | core.hh | diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/unittest/ | ||
H A D | stattest.cc | diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
/gem5/src/arch/x86/ | ||
H A D | system.hh | diff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects. |
/gem5/src/dev/virtio/ | ||
H A D | fs9p.cc | diff 12076:d6fa15da87cd Wed Mar 01 08:50:00 EST 2017 Anouk Van Laer <anouk.vanlaer@arm.com> dev, virtio: Use of Unix socket for virtIO 9P device This commit adds support for diod to use a unix socket, rather than a TCP port. We don't rely on the IP-based connection as we directly use pipes to interact with diod. This allows it to work on any system, even if the specific port is taken by another diod instance (or similar). Secondly, the Unix socket could in theory be used to debug. However, this functionality has not been tested. Change-Id: I616e0ad8768da1dfc867de3af98cdfbb22a72d63 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2820 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/cpu/minor/ | ||
H A D | fetch1.cc | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
H A D | MinorCPU.py | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
H A D | scoreboard.cc | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
H A D | scoreboard.hh | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/dev/arm/ | ||
H A D | rtc_pl031.cc | diff 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | gic_v2.hh | 13014:a4f71c3dc602 Thu Aug 30 09:50:00 EDT 2018 Ciro Santilli <ciro.santilli@arm.com> dev-arm: rename Pl390 to GicV2 The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | gic_v2.cc | 13014:a4f71c3dc602 Thu Aug 30 09:50:00 EDT 2018 Ciro Santilli <ciro.santilli@arm.com> dev-arm: rename Pl390 to GicV2 The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/configs/common/ | ||
H A D | PlatformConfig.py | diff 11688:725fef71f376 Wed Oct 26 14:50:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> config: Break out base options for usage with NULL ISA This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported. |
/gem5/configs/example/ | ||
H A D | ruby_gpu_random_test.py | diff 11688:725fef71f376 Wed Oct 26 14:50:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> config: Break out base options for usage with NULL ISA This patch breaks out the most basic configuration options into a set of base options, to allow them to be used also by scripts that do not involve any ISA, and thus no actual CPUs or devices. The patch also fixes a few modules so that they can be imported in a NULL build, and avoid dragging in FSConfig every time Options is imported. |
/gem5/src/arch/alpha/linux/ | ||
H A D | linux.hh | diff 13536:77e19417e723 Wed Jan 09 09:50:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> sim-se: Refactor clone to avoid most ifdefs Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
/gem5/src/arch/arm/ | ||
H A D | decoder.hh | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
H A D | decoder.cc | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | neon64.isa | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
/gem5/src/arch/hsail/ | ||
H A D | gen.py | diff 11737:50eceddc2286 Fri Dec 02 18:01:00 EST 2016 Brandon Potter <brandon.potter@amd.com> hsail: add popcount type and generate popcount instructions |
/gem5/src/arch/riscv/linux/ | ||
H A D | linux.hh | diff 13536:77e19417e723 Wed Jan 09 09:50:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> sim-se: Refactor clone to avoid most ifdefs Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
/gem5/src/arch/sparc/linux/ | ||
H A D | linux.hh | diff 13536:77e19417e723 Wed Jan 09 09:50:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> sim-se: Refactor clone to avoid most ifdefs Some parts of clone are architecture dependent. In some cases, we are able to use architecture-specific helper functions or register aliases. However, there is still some architecture-specific that is protected by ifdefs in the common clone implementation. Move these architecture-specific bits to the architecture-specific OS class instead to avoid these ifdefs and make the code a bit more readable. Change-Id: Ia0903d738d0ba890863bddfa77e3b717db7f45de Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15435 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> |
/gem5/src/cpu/simple/ | ||
H A D | TimingSimpleCPU.py | diff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | tagged.cc | diff 13551:f352df8e2863 Sat Nov 17 18:50:00 EST 2018 Javier Bueno <javier.bueno@metempsy.com> mem-cache: virtual address support for prefetchers Prefetchers can be configured to operate with virtual or physical addreses. The option can be configured through the "use_virtual_addresses" parameter of the Prefetcher object. Change-Id: I4f8c3687988afecc8a91c3c5b2d44cc0580f72aa Reviewed-on: https://gem5-review.googlesource.com/c/14416 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
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