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/gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/ | ||
H A D | system.pc.com_1.terminal | diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. |
/gem5/src/base/ | ||
H A D | cp_annotate.hh | diff 7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values. |
H A D | socket.cc | diff 12010:032f2717dfb7 Fri May 05 19:50:00 EDT 2017 Gabe Black <gabeblack@google.com> base: Teach the socket listeners how to bind to the loopback. The loopback device will allow access to various services like remote GDB debugging, connecting to the terminal, etc., without letting external agents like port scanners connect and disrupting the simulation. Change-Id: I76dccbf152fa278ae9f342b25f7e345a1329fbe4 Reviewed-on: https://gem5-review.googlesource.com/3080 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/ | ||
H A D | simerr | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/ | ||
H A D | config.ini | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/ | ||
H A D | config.ini | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ | ||
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/ | ||
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/ | ||
H A D | config.ini | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/ | ||
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/ | ||
H A D | config.ini | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/ | ||
H A D | simout | diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
/gem5/src/arch/hsail/insts/ | ||
H A D | decl.hh | diff 11737:50eceddc2286 Fri Dec 02 18:01:00 EST 2016 Brandon Potter <brandon.potter@amd.com> hsail: add popcount type and generate popcount instructions |
/gem5/src/cpu/ | ||
H A D | timing_expr.cc | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/systemc/core/ | ||
H A D | sc_interface.cc | diff 13251:5cb61fcb0ae2 Sat Sep 22 09:50:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add a warning to sc_interface::default_event. The default implementation returns a dummy event, but in the Accellera implementation it also prints a warning. Print a warning as well, so that the output matches for the tests. Change-Id: I1ae2755685515c3fe538f4075af396e963cf155d Reviewed-on: https://gem5-review.googlesource.com/c/12970 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/systemc/ext/core/ | ||
H A D | _using.hh | diff 12943:12c1004709d4 Mon Jun 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add the nonstandard sc_join class and sc_thread_handle type. Change-Id: I09905bad4797d9c456229afe601006ce16977394 Reviewed-on: https://gem5-review.googlesource.com/11353 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/cpu/minor/ | ||
H A D | fetch1.hh | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
/gem5/src/dev/arm/ | ||
H A D | amba_fake.cc | diff 12772:362544959c40 Mon Jun 04 12:50:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> dev-arm: Fix the address range for some I/O devices Previously, many devices were incorrecty configured to respond to an address range of size 0xfff. This changes fixes this and sets it to 0x1000. Change-Id: I4b027a27adf60ceae4859e287d7f34443b398752 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11116 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/configs/topologies/ | ||
H A D | Pt2Pt.py | diff 9148:a7a72f42919e Fri Aug 10 14:50:00 EDT 2012 Jason Power <powerjg@cs.wisc.edu> Ruby: Clean up topology changes This patch moves instantiateTopology into Ruby.py and removes the mem/ruby/network/topologies directory. It also adds some extra inheritance to the topologies to clean up some issues in the existing topologies. |
/gem5/src/arch/arm/insts/ | ||
H A D | fplib.cc | diff 10272:336c7d36ac00 Tue Mar 11 10:50:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> arm: remove dead code fplib mul64x64 |
/gem5/src/arch/x86/ | ||
H A D | X86System.py | diff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects. |
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