Searched hist:50 (Results 101 - 125 of 671) sorted by relevance
| /gem5/ext/testlib/ | ||
| H A D | fixture.py | diff 14141:b3ceff47211a Tue Jun 18 06:50:00 EDT 2019 Nikos Nikoleris <nikos.nikoleris@arm.com> tests: Refactor the Gem5Fixture to derive from UniqueFixture Gem5Fixture is used to define a fixture for building the gem5 binary. Most tests are expected to define their own Gem5Fixture, however, as some might depend on the same binary (e.g., ./build/ARM/gem5.opt), they will try to re-define a fixture for the same target. This patchset changes Gem5Fixture to derive from UniqueFixture. In addition, this patchset changes the way global fixtures are discovered to work with the new Gem5Fixture class. Instead of enumerating them when test definitions are loaded, we do so after the tests have been filtered according to specified tags (e.g., include opt variant, exclude fast, debug variants). Change-Id: Ie868a7e18ef6c3271f3c8a658229657cd43997cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19251 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> |
| /gem5/tests/gem5/m5_util/ | ||
| H A D | test_exit.py | diff 14142:e732d3191b7c Wed May 29 06:50:00 EDT 2019 Nikos Nikoleris <nikos.nikoleris@arm.com> tests: Add support for downloaded archive fixtures This changes add support for specifying fixtures that download archives and uncompress them to the desired directory. Change-Id: Ib3f6ee111b8d6130200507cbd170ecaf9fb39445 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18988 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/tests/gem5/hello_se/ | ||
| H A D | test_hello_se.py | diff 14142:e732d3191b7c Wed May 29 06:50:00 EDT 2019 Nikos Nikoleris <nikos.nikoleris@arm.com> tests: Add support for downloaded archive fixtures This changes add support for specifying fixtures that download archives and uncompress them to the desired directory. Change-Id: Ib3f6ee111b8d6130200507cbd170ecaf9fb39445 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18988 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/ | ||
| H A D | move_non_temporal.py | diff 14287:1c9774d969ac Wed Sep 18 19:50:00 EDT 2019 Hoa Nguyen <hoanguyen@ucdavis.edu> arch-x86: Change warn to warn_once for NT instructions Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/ | ||
| H A D | move_non_temporal.py | diff 14287:1c9774d969ac Wed Sep 18 19:50:00 EDT 2019 Hoa Nguyen <hoanguyen@ucdavis.edu> arch-x86: Change warn to warn_once for NT instructions Change-Id: I50353716f2a913b9b106b140644d95991879f662 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21039 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/ | ||
| H A D | config.ini | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
| H A D | simout | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
| /gem5/src/cpu/minor/ | ||
| H A D | SConsopts | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
| H A D | func_unit.cc | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
| /gem5/src/mem/ruby/network/simple/ | ||
| H A D | SConscript | diff 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. |
| /gem5/configs/boot/ | ||
| H A D | devtime.rcS | 1370:2063295aa1ab Thu Feb 03 23:50:00 EST 2005 Ali Saidi <saidi@eecs.umich.edu> Add Monet configuration, update p4 parameters, couple of typo fixes dev/tsunami_cchip.cc: add a fake register to tsunami that we can do 32bit reads to. Warn on access. |
| /gem5/util/stats/ | ||
| H A D | chart.py | 2006:3ca085495c69 Tue Nov 22 21:50:00 EST 2005 Nathan Binkert <binkertn@umich.edu> Major improvements in the graph output code. Mostly adding more options, making existing options more visible and dealing with holes in data better. util/stats/barchart.py: - move the options for BarChart to a base class ChartOptions so they can be more easily set and copied. - add an option to set the chart size (so you can adjust the aspect ratio) - don't do the add_subplot thing, use add_axes directly so we can affect the size of the figure itself to make room for the legend - make the initial array bottom floating point so we don't lose precision - add an option to set the limits on the y axis - use a figure legend instead of an axes legend so we can put the legend outside of the actual chart. Also add an option to set the fontsize of the legend. - initial hack at outputting csv files util/stats/db.py: don't print out an error when the run is missing from the database just return None, the error will be print elsewhere. util/stats/output.py: - make StatOutput derive from ChartOptions so that it's easier to set default chart options. - make the various output functions (graph, display, etc.) take the name of the data as a parameter instead of making it a parameter to __init__. This allows me to create the StatOutput object with generic parameters while still being able to specialize the name after the fact - add support for graph_group and graph_bars to be applied to multiple configuration groups. This results in a cross product of the groups to be generated and used. - flush the html file output as we go so that we can load the file while graphs are still being generated. - make the proxy a parameter to the graph function so the proper system's data can be graphed - for any groups or bars that are completely missing, remove them from the graph. This way, if we decide not to do a set of runs, there won't be holes in the data. - output eps and ps by default in addition to the png. util/stats/profile.py: - clean up the data structures that are used to store the function profile information and try our best to avoid keeping extra data around that isn't used. - make get() return None if a job is missing so we know it was missing rather than the all zeroes thing. - make the function profile categorization stuff total up to 100% - Fixup the x-axis and y-axis labels. - fix the dot file output stuff. util/stats/stats.py: support the new options stuff for StatOutput |
| /gem5/src/arch/alpha/ | ||
| H A D | decoder.hh | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
| /gem5/src/arch/power/ | ||
| H A D | decoder.hh | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
| /gem5/src/mem/ruby/profiler/ | ||
| H A D | SConscript | diff 8492:1ad244a20877 Mon Aug 08 11:50:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> BuildEnv: Eliminate RUBY as build environment variable This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled. |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/ | ||
| H A D | config.ini | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> diff 10848:e61f847e74fd Sat May 23 08:50:00 EDT 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm, stats: Update stats to reflect changes to generic timer The addition of a virtual timer affects stats in minor and o3. diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
| H A D | simout | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> diff 10848:e61f847e74fd Sat May 23 08:50:00 EDT 2015 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm, stats: Update stats to reflect changes to generic timer The addition of a virtual timer affects stats in minor and o3. diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. diff 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes |
| /gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/ | ||
| H A D | simerr | diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. |
| /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/ | ||
| H A D | simerr | diff 10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower. |
| /gem5/build_opts/ | ||
| H A D | ARM | diff 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
| /gem5/src/arch/mips/ | ||
| H A D | decoder.hh | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | neon64.isa | diff 11165:d90aec9435bd Fri Oct 09 15:50:00 EDT 2015 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> isa: Add parameter to pick different decoder inside ISA The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time. |
| /gem5/configs/topologies/ | ||
| H A D | Crossbar.py | diff 9148:a7a72f42919e Fri Aug 10 14:50:00 EDT 2012 Jason Power <powerjg@cs.wisc.edu> Ruby: Clean up topology changes This patch moves instantiateTopology into Ruby.py and removes the mem/ruby/network/topologies directory. It also adds some extra inheritance to the topologies to clean up some issues in the existing topologies. |
| /gem5/src/python/m5/util/ | ||
| H A D | terminal.py | 7816:b5003ac75977 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: show sources and targets when building, and colorize output. I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story. |
| /gem5/src/sim/ | ||
| H A D | TickedObject.py | 10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark | Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) | simple | o3 | minor | timing | timing | timing ---------------+--------+--------+-------- 10.linux-boot | 169 | 1883 | 1075 10.mcf | 117 | 967 | 491 20.parser | 668 | 6315 | 3146 30.eon | 542 | 3413 | 2414 40.perlbmk | 2339 | 20905 | 11532 50.vortex | 122 | 1094 | 588 60.bzip2 | 2045 | 18061 | 9662 70.twolf | 207 | 2736 | 1036 |
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