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/gem5/configs/common/
H A DSimulation.pydiff 3514:b166ee5dce91 Thu Nov 09 15:05:00 EST 2006 Kevin Lim <ktlim@umich.edu> Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.

configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

However the O3CPU must always use caches, so a check for that must still exist.

Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
/gem5/configs/example/
H A Dfs.pydiff 3514:b166ee5dce91 Thu Nov 09 15:05:00 EST 2006 Kevin Lim <ktlim@umich.edu> Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.

configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

However the O3CPU must always use caches, so a check for that must still exist.

Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.
H A Dse.pydiff 3514:b166ee5dce91 Thu Nov 09 15:05:00 EST 2006 Kevin Lim <ktlim@umich.edu> Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.

configs/common/Simulation.py:
Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.

However the O3CPU must always use caches, so a check for that must still exist.

Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU.
configs/example/fs.py:
configs/example/se.py:
Atomic CPU now handles caches.

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