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/gem5/src/cpu/ | ||
H A D | base_dyn_inst_impl.hh | diff 3326:d9cc6bae9d77 Mon Oct 23 14:00:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Add in support for LL/SC in the O3 CPU. Needs to be fully tested. src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. |
H A D | base_dyn_inst.hh | diff 3326:d9cc6bae9d77 Mon Oct 23 14:00:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Add in support for LL/SC in the O3 CPU. Needs to be fully tested. src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. |
/gem5/src/cpu/o3/ | ||
H A D | lsq_unit.hh | diff 3326:d9cc6bae9d77 Mon Oct 23 14:00:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Add in support for LL/SC in the O3 CPU. Needs to be fully tested. src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. |
H A D | lsq_unit_impl.hh | diff 3326:d9cc6bae9d77 Mon Oct 23 14:00:00 EDT 2006 Kevin Lim <ktlim@umich.edu> Add in support for LL/SC in the O3 CPU. Needs to be fully tested. src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. |
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