Searched hist:31 (Results 201 - 225 of 1011) sorted by relevance
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. diff 9490:e6a09d97bdc9 Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default. |
/gem5/src/base/ | ||
H A D | str.cc | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/arch/sparc/solaris/ | ||
H A D | process.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak |
/gem5/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak |
/gem5/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak |
/gem5/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak |
/gem5/src/arch/alpha/ | ||
H A D | SConscript | diff 8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS. diff 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. diff 3457:7479ebe49444 Tue Oct 31 16:02:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR. diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/ext/drampower/src/ | ||
H A D | MemCommand.h | diff 11555:2efa95cf8504 Fri Jul 01 11:31:00 EDT 2016 Matthias Jung <jungma@eit.uni-kl.de> ext: Update DRAMPower Sync DRAMPower to external tool This patch syncs the DRAMPower library of gem5 to the external one on github (https://github.com/ravenrd/DRAMPower) of which I am a maintainer. The version used is the commit: 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. May. 2016. Committed by Jason Lowe-Power <jason@lowepower.com> |
H A D | Utils.h | diff 11555:2efa95cf8504 Fri Jul 01 11:31:00 EDT 2016 Matthias Jung <jungma@eit.uni-kl.de> ext: Update DRAMPower Sync DRAMPower to external tool This patch syncs the DRAMPower library of gem5 to the external one on github (https://github.com/ravenrd/DRAMPower) of which I am a maintainer. The version used is the commit: 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. May. 2016. Committed by Jason Lowe-Power <jason@lowepower.com> |
/gem5/ext/libelf/ | ||
H A D | SConscript | diff 8737:770ccf3af571 Tue Jan 31 00:05:00 EST 2012 Koan-Sin Tan <koansin.tan@gmail.com> clang: Enable compiling gem5 using clang 2.9 and 3.0 This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places. diff 4504:936dfda07b50 Thu May 31 18:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> This is probably a more scons like way to do this diff 4500:068356f4fa81 Thu May 31 16:45:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> obey the m5 style diff 4496:7fe59ed05a61 Thu May 31 15:33:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> check that m4 is available before trying to use it |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | m5ops.isa | diff 8734:79592b2b1d55 Tue Jan 31 10:46:00 EST 2012 Dam Sunwoo <dam.sunwoo@arm.com> util: implements "writefile" gem5 op to export file from guest to host filesystem Usage: m5 writefile <filename> File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders. |
/gem5/src/systemc/core/ | ||
H A D | sched_event.hh | diff 13144:61e0f3230787 Fri Aug 31 19:18:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Store timed notifications in a list instead of a set. This has three advantages. First, the data structure doesn't have to try to keep track of whether or not an event is already listed there. Second, it's easier to delete an item by storing an iterator for it when it gets inserted. Third, the ordering of events is not dependent on the arbitrary ordering of the set, it's bsaed on the fixed order the events get added to the list. One part of this change makes ScEvent-s keep track of what list they're on, and handle their own insertion and deletion when they're scheduled or descheduled. A side effect of that is that it's no longer safe to simply use a range based for loop to loop over all of an ScEvent and deschedule all its events or to run then (which deschedules them internally once they execute). That can be avoided by looping until the list is empty, and operating on the first element. As the first element is processed and removed from the list, the next element will become first and will get picked up in the next iteration. Change-Id: Icad51a63f153297c88e65f85d22ac721e6c571d8 Reviewed-on: https://gem5-review.googlesource.com/c/12456 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/arm/isa/decoder/ | ||
H A D | decoder.isa | diff 10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. |
/gem5/src/cpu/simple/ | ||
H A D | SConscript | diff 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. |
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | random_rp.cc | diff 12718:abad79926b86 Thu May 31 08:05:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Fix RandomReplData Random replacement policy's data was being instantiated with the incorrect class. Change-Id: Ib573a6b5a63868d6069997c6279bec3b10c6b9b9 Reviewed-on: https://gem5-review.googlesource.com/10623 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/ext/drampower/src/libdrampower/ | ||
H A D | LibDRAMPower.h | diff 11555:2efa95cf8504 Fri Jul 01 11:31:00 EDT 2016 Matthias Jung <jungma@eit.uni-kl.de> ext: Update DRAMPower Sync DRAMPower to external tool This patch syncs the DRAMPower library of gem5 to the external one on github (https://github.com/ravenrd/DRAMPower) of which I am a maintainer. The version used is the commit: 902a00a1797c48a9df97ec88868f20e847680ae6 from 07. May. 2016. Committed by Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/arm/ | ||
H A D | isa_device.hh | diff 10609:ae5582819481 Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <andreas.sandberg@arm.com> arm: Add support for filtering in the PMU This patch adds support for filtering events in the PMU. In order to do so, it updates the ISADevice base class to forward an ISA pointer to ISA devices. This enables such devices to access the MiscReg file to determine the current execution level. |
H A D | isa_device.cc | diff 10609:ae5582819481 Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <andreas.sandberg@arm.com> arm: Add support for filtering in the PMU This patch adds support for filtering events in the PMU. In order to do so, it updates the ISADevice base class to forward an ISA pointer to ISA devices. This enables such devices to access the MiscReg file to determine the current execution level. |
/gem5/src/unittest/ | ||
H A D | genini.py | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/util/ | ||
H A D | oprofile-top.py | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
H A D | regress | diff 9843:1ddfb0679c75 Wed Aug 21 20:31:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> util/regress: set --no-lto on regressions See comment for motivation. diff 7047:04d988a19ae9 Tue Mar 23 19:31:00 EDT 2010 Nathan Binkert <nate@binkert.org> regress: add some new options add -n/--no-exec which doesn't execute scons, but just prints the command line add -j0 which tries to calculate how many cpus you have add -D/--build-dir to specify a build directory other than ./build diff 4961:31f1d816dc26 Mon Aug 13 23:40:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Regression: See if using subprocess instead of os.system and erroring immediately will stop regression randomly hanging. diff 3077:31da34df3139 Fri Aug 25 13:04:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Update for new regression test structure. |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/ | ||
H A D | move.py | diff 14033:a1cb162f68d9 Fri May 31 15:02:00 EDT 2019 Brandon Potter <brandon.potter@amd.com> x86: fix movsd bug on %xmm register The movsd instruction should zero out half the register, but does not do it. This changeset adds the necessary microop to the instruction to cause correct behavior. Change-Id: I5278da3634c78a97ed0586f687a36c6dc5a34c60 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19068 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/mem/cache/prefetch/ | ||
H A D | access_map_pattern_matching.hh | diff 13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Reviewed-on: https://gem5-review.googlesource.com/c/16383 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | SConscript | diff 13772:31b71dadc472 Thu Mar 07 09:42:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Indirect Memory Prefetcher Reference: Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas. 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48). ACM, New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807 Change-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> diff 13700:56fa28e6fab4 Thu Jan 31 10:24:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Slim AMPM Prefetcher Reference: Towards Bandwidth-Efficient Prefetching with Slim AMPM. Young, V., & Krishna, A. (2015). The 2nd Data Prefetching Championship. Slim AMPM is composed of two prefetchers, the DPCT and the AMPM (both already in gem5). Change-Id: I6e868faf216e3e75231cf181d59884ed6f0d382a Reviewed-on: https://gem5-review.googlesource.com/c/16383 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> diff 13667:e3ae3619b9ab Tue Feb 05 17:31:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Delta Correlating Prediction Tables Prefetcher Reference: Multi-level hardware prefetching using low complexity delta correlating prediction tables with partial matching. Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010. In Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers (HiPEAC'10) Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d Reviewed-on: https://gem5-review.googlesource.com/c/16062 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> diff 10623:b9646f4546ad Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Rework the structuring of the prefetchers Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure. |
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