Searched hist:2012 (Results 451 - 475 of 1124) sorted by relevance

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/gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-atomic/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/
H A Dsimerr8889:2e38fd9937a9 Fri Mar 09 09:59:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Make some basic regression tests for CheckerCPU

Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/
H A Dsimerr8889:2e38fd9937a9 Fri Mar 09 09:59:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Make some basic regression tests for CheckerCPU

Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/
H A Dsimerr8802:ef66a9083bc4 Sat Jan 28 10:24:00 EST 2012 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make both SE and FS tests available all the time.
/gem5/src/kern/
H A Doperatingsystem.ccdiff 9143:db55c4b5136e Mon Aug 06 19:55:00 EDT 2012 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: clean up open() code a bit.
/gem5/src/mem/ruby/common/
H A DTypeDefines.hhdiff 9231:cecc64db9b3b Tue Sep 18 23:49:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate typedef integer_t
diff 9209:f9633070689b Tue Sep 11 10:24:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> Ruby: Use uint32_t instead of uint32 everywhere
diff 9208:2451e60d4555 Tue Sep 11 10:23:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> Ruby: Use uint8_t instead of uint8 everywhere
diff 9171:ae88ecf37145 Mon Aug 27 02:00:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.
/gem5/src/arch/arm/insts/
H A Dbranch.hhdiff 8909:7fa0a081f12f Wed Mar 21 11:34:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clean up condCodes in IT blocks.
/gem5/src/dev/arm/
H A Dtimer_cpulocal.hhdiff 9525:0587c8983d47 Thu Oct 25 09:05:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Create a GIC base class and make the PL390 derive from it

This patch moves the GIC interface to a separate base class and makes
all interrupt devices use that base class instead of a pointer to the
PL390 implementation. This allows us to have multiple GIC
implementations. Future implementations will allow in-kernel GIC
implementations when using hardware virtualization.
diff 9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
diff 9235:5aa4896ed55a Wed Sep 19 06:15:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> AddrRange: Transition from Range<T> to AddrRange

This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.
diff 9193:e2c5da9e28cc Fri Sep 07 15:20:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> dev: Fix bifield definition in timer_cpulocal.hh

Bitfield definition in the local timer model for ARM had the bitfield
range numbers reversed which could lead to buggy behavior.
/gem5/src/arch/arm/
H A Ddecoder.hhdiff 9024:5851586f399c Sat May 26 16:45:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> ISA,CPU: Generalize and split out the components of the decode cache.

This will allow it to be specialized by the ISAs. The existing caching scheme
is provided by the BasicDecodeCache in the GenericISA namespace and is built
from the generalized components.
diff 9023:e9201a7bce59 Sat May 26 16:44:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.
diff 9022:bb25e7646c41 Fri May 25 03:55:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> ISA: Make the decode function part of the ISA's decoder.
9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA.

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