Searched hist:2010 (Results 126 - 150 of 929) sorted by relevance

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/gem5/src/arch/x86/isa/insts/simd64/integer/
H A Ddata_conversion.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dexit_media_state.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/
H A Dextract_and_insert.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dshuffle_and_swap.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/
H A Dmove_mask.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/
H A Dexclusive_or.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dpor.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd64/integer/shift/
H A Dleft_logical_shift.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dright_arithmetic_shift.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dright_logical_shift.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/x87/arithmetic/
H A Ddivision.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dmultiplication.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/arm/insts/
H A Dpred_inst.ccdiff 7143:c81f34f9e075 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of obsoleted predicated inst formats, etc.
diff 7142:c63c06703d0f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement disassembly for the new data processing classes.
diff 7110:7d27bd3e7ffb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for 32 bit thumb data processing immediate instructions.
H A Dmem.ccdiff 7429:af0e80844b14 Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Make some of the trace code more compact
diff 7428:eea9a618c882 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.
diff 7313:b0262368daa0 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the SRS instruction.
diff 7312:03016344f54e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for SRS.
diff 7291:2d21be52e57f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for the RFE instruction.
diff 7279:157b02cc0ba1 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Explicitly keep track of the second destination for double loads/stores.
diff 7205:e3dfcdf19561 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the swp and swpb instructions.
diff 7132:83b433d6e600 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Remove the special naming for the new memory instructions.
These are the only memory instructions now.
diff 7131:ab3a70a37ca8 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Eliminate the old memory formats which are no longer used.
diff 7118:444a3e126366 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement a new set of base classes for non macro memory instructions.
/gem5/src/arch/arm/isa/insts/
H A Dmult.isadiff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
diff 7422:feddb9077def Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode to specialized conditional/unconditional versions of instructions.

This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
diff 7229:ed81380fd089 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Fix signed most significant multiply instructions.
diff 7228:09302e193402 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Fix multiply overflow flag setting.
diff 7196:80c72fc2063b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Fix multiply operations.

These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
diff 7162:97fe2d298f3e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Remove special naming for the new version of multiply.
7160:3f4333b1d4af Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all integer multiply instructions.
H A Dmem.isadiff 7646:a444dbee8c07 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.
diff 7590:27dbb92bbad5 Mon Aug 23 12:18:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Clean up the ISA desc portion of the ARM memory instructions.
diff 7422:feddb9077def Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode to specialized conditional/unconditional versions of instructions.

This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.
diff 7313:b0262368daa0 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the SRS instruction.
diff 7303:6b70985664c8 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the strex instructions.
diff 7294:fda2c00880db Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the V7 version of alignment checking.
diff 7292:f4d99c45743e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the RFE instruction.
diff 7279:157b02cc0ba1 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Explicitly keep track of the second destination for double loads/stores.
diff 7205:e3dfcdf19561 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the swp and swpb instructions.
diff 7133:4a1af4580b7d Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the templates for predicated instructions into a separate file.
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.
H A Dinsts.isadiff 7732:a2c660de7787 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for M5 ops in the ARM ISA
diff 7639:8c09b7ff5b57 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all ARM SIMD instructions.
diff 7322:49cfb31a2fb7 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the VMSR instruction.
diff 7318:64352bcff9f3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the sdiv instruction.
diff 7205:e3dfcdf19561 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the swp and swpb instructions.
diff 7199:3e96b80d1b55 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement SVC (was SWI) outside of the decoder.
diff 7160:3f4333b1d4af Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement all integer multiply instructions.
diff 7151:672a20bbd4ff Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement branch instructions external to the decoder.
diff 7138:5dff7c15008f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement data processing instructions external to the decoder.
diff 7134:60fe8a00b36e Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Reimplement load/store multiple external to the decoder.
H A Ddiv.isadiff 7760:e93e7e0caae1 Mon Nov 15 15:04:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
diff 7361:e18233acf0be Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make integer division by zero return a fault.
diff 7319:d4e9a5e31a38 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the udiv instruction.
7318:64352bcff9f3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the sdiv instruction.
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.ccdiff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class
diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
diff 7048:2ab58c54de63 Wed Mar 24 01:49:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: continue style pass
/gem5/src/cpu/testers/directedtest/
H A DSConscript7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
/gem5/src/cpu/testers/rubytest/
H A DSConscript7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
/gem5/src/mem/slicc/ast/
H A DLiteralExprAST.pydiff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
/gem5/src/arch/arm/isa/formats/
H A Dbasic.isadiff 7167:a28390624772 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Split out the "basic" templates and format.
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dset_byte_on_condition.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dascii_adjust.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly

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