Searched hist:2009 (Results 451 - 475 of 951) sorted by relevance

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/gem5/src/arch/alpha/
H A Disa.hhdiff 6678:34191eea18c1 Sat Oct 17 04:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Fix compilation.
diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
diff 6330:786136379872 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Pull the MiscRegFile fully into the ISA object.
6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
/gem5/src/arch/mips/
H A DMipsTLB.pydiff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
/gem5/src/arch/sparc/
H A Disa.hhdiff 6337:cac56cd6b015 Fri Jul 10 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Set up a lookup table for integer register flattening.
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:

real 14m45.951s
user 13m57.528s
sys 0m3.452s

to:

real 12m19.777s
user 12m2.685s
sys 0m2.420s
diff 6335:a08470cb53e5 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Fold the MiscRegFile all the way into the ISA object.
diff 6331:d947798df4a1 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
H A DSparcTLB.pydiff 6022:410194bb3049 Thu Apr 09 01:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
/gem5/src/arch/x86/
H A Disa.ccdiff 6712:b95abe00dd9d Wed Nov 04 19:57:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compile problems pointed out by gcc 4.4
diff 6359:1e4908b3e28e Fri Jul 17 03:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Shift some register flattening work into the decoder.
diff 6336:25635830e33c Thu Jul 09 23:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fold the MiscRegFile all the way into the ISA object.
6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
H A Dinterrupts.hhdiff 6137:d3ee4e0d690c Sun Apr 26 05:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APICs register themselves with the IO APIC.
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
diff 6136:4f8af2f3185f Sun Apr 26 05:06:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Record the initial APIC ID which identifies an APIC in M5.
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
diff 6101:860df2c586a3 Sun Apr 19 16:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the functions that manipulate large bit arrays in the local APIC.
diff 6069:cb5b778785a6 Sun Apr 19 07:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement broadcast IPIs.
diff 6066:a9fe0813039f Sun Apr 19 06:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Only recognize the first startup IPI after INIT or reset.
diff 6064:46d327d42036 Sun Apr 19 06:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a function which gets called when an interrupt message has been delivered.
diff 6050:852ba59fa8d9 Sun Apr 19 06:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: The startup IPI delivery mode is not reserved.
diff 6041:949a8304e7f9 Sun Apr 19 05:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set the local APIC ID to something meaningful.
diff 5810:606de5b3d116 Sun Jan 25 23:29:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Add a setCPU function to the interrupt objects.
/gem5/src/dev/mips/
H A DMalta.pydiff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
H A Dmalta_io.ccdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
H A Dmalta.ccdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
/gem5/src/python/m5/util/
H A Dsmartdict.py6654:4c84e771cca7 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> python: Move more code into m5.util allow SCons to use that code.
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
/gem5/src/sim/
H A Dinsttracer.hhdiff 6364:a71fd8e252b7 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Tracing: Add accessors so tracers can get at data in trace records.
diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 5784:8a28646c4bc2 Wed Jan 07 01:34:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Tracing: Make tracing aware of macro and micro ops.
/gem5/src/arch/power/
H A Dstacktrace.hh6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dprocess.hhdiff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array.

When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.

All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/base/
H A Dmatch.ccdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
/gem5/src/arch/arm/
H A Dinterrupts.cc6757:d86d3d6e5326 Tue Nov 17 19:02:00 EST 2009 Ali Saidi <Ali.Saidi@ARM.com> ARM: Boilerplate full-system code.
H A Disa.hhdiff 6745:cdc62b81747e Sat Nov 14 22:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Hook up the moded versions of the SPSR.

These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
diff 6735:6437ad24a8a0 Tue Nov 10 23:34:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Implement fault classes.

Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
diff 6726:a5322e816a2a Sun Nov 08 18:49:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Support forcing load/store multiple to use user registers.
diff 6723:ea7c71a3433a Sun Nov 08 05:01:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add in more bits for the mon mode.
diff 6719:260676453f66 Sun Nov 08 03:54:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Initialize processes in user mode.

I accidentally left in a change to test using int registers in system mode.
This change reverts that.
diff 6718:2a131d15ec34 Sun Nov 08 03:07:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Implement the shadow registers using register flattening.
diff 6678:34191eea18c1 Sat Oct 17 04:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ISA: Fix compilation.
diff 6401:4e9d4c206930 Mon Jul 27 03:52:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Initialize the CPSR so that we're in user mode.
diff 6333:9425c8a86e5c Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fold the MiscRegFile all the way into the ISA object.
diff 6328:67dbc192f692 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Collapse ARM and MIPS regfile directories.
/gem5/src/dev/x86/
H A DI8254.pydiff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
/gem5/src/cpu/pred/
H A Dras.ccdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
6226:f1076450ab2b Fri Jun 05 00:50:00 EDT 2009 Nathan Binkert <nate@binkert.org> move: put predictor includes and cc files into the same place
/gem5/src/cpu/
H A Dprofile.hhdiff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
/gem5/src/mem/ruby/common/
H A DAddress.ccdiff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/kern/
H A DSConscriptdiff 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc
diff 5793:321f79ddb500 Tue Jan 13 17:17:00 EST 2009 Nathan Binkert <nate@binkert.org> SCons: centralize the Dir() workaround for newer versions of scons.
Scons bug id: 2006 M5 Bug id: 308
/gem5/src/mem/ruby/network/simple/
H A DPerfectSwitch.ccdiff 6846:60e0df8086f0 Thu Sep 17 18:39:00 EDT 2009 Polina Dudnik <pdudnik@cs.wisc.edu> Functionality migrated to sequencer.
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6288:083a6806dd96 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: apply some fixes that were overwritten by the recent ruby import.
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6156:76de2027b8ad Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: clean up a few warnings
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/alpha/isa/
H A Dpal.isadiff 6181:19fedb1e5ded Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
diff 6076:e141cc7896ce Sun Apr 19 07:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Memory: Rename LOCKED for load locked store conditional to LLSC.
/gem5/src/arch/alpha/linux/
H A Dlinux.hhdiff 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hhdiff 6748:dc2adb7ffff5 Sat Nov 14 22:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Write some functions to write to the CPSR and SPSR for instructions.
diff 6306:fe1004d455b2 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Tune up predicated instruction decoding.
diff 6264:588457e03a81 Sat Jun 27 03:30:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Show more information when disassembling data processing intstructions.
This will need more work, but it should be a lot closer.
diff 6263:981fc6fba01a Sat Jun 27 03:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Show branch targets relative to the nearest symbol.
diff 6262:43950710afdc Sat Jun 27 03:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Write a function for printing mnemonics and predicates.
diff 6255:7abd88201a71 Mon Jun 22 01:51:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify some utility functions.
diff 6254:8abc40611938 Mon Jun 22 01:50:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Move util functions out of the isa desc.
6253:988a001820f8 Sun Jun 21 20:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify the ISA desc by pulling some classes out of it.

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