15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Rick Strong 305222Sksewell@umich.edu */ 315222Sksewell@umich.edu 325222Sksewell@umich.edu/** @file 335222Sksewell@umich.edu * Implementation of Malta platform. 345222Sksewell@umich.edu */ 355222Sksewell@umich.edu 3611793Sbrandon.potter@amd.com#include "dev/mips/malta.hh" 3711793Sbrandon.potter@amd.com 385222Sksewell@umich.edu#include <deque> 395222Sksewell@umich.edu#include <string> 405222Sksewell@umich.edu#include <vector> 415222Sksewell@umich.edu 425222Sksewell@umich.edu#include "cpu/intr_control.hh" 438739Sgblack@eecs.umich.edu#include "debug/Malta.hh" 445222Sksewell@umich.edu#include "dev/mips/malta_cchip.hh" 458229Snate@binkert.org#include "dev/mips/malta_io.hh" 465222Sksewell@umich.edu#include "params/Malta.hh" 475222Sksewell@umich.edu#include "sim/system.hh" 485222Sksewell@umich.edu 495222Sksewell@umich.eduusing namespace std; 505222Sksewell@umich.edu 515222Sksewell@umich.eduMalta::Malta(const Params *p) 525222Sksewell@umich.edu : Platform(p), system(p->system) 535222Sksewell@umich.edu{ 545222Sksewell@umich.edu for (int i = 0; i < Malta::Max_CPUs; i++) 555222Sksewell@umich.edu intr_sum_type[i] = 0; 565222Sksewell@umich.edu} 575222Sksewell@umich.edu 585222Sksewell@umich.eduvoid 595222Sksewell@umich.eduMalta::postConsoleInt() 605222Sksewell@umich.edu{ 616379Sgblack@eecs.umich.edu //see {Linux-src}/arch/mips/mips-boards/sim/sim_setup.c 626379Sgblack@eecs.umich.edu io->postIntr(0x10/*HW4*/); 635222Sksewell@umich.edu} 645222Sksewell@umich.edu 655222Sksewell@umich.eduvoid 665222Sksewell@umich.eduMalta::clearConsoleInt() 675222Sksewell@umich.edu{ 686379Sgblack@eecs.umich.edu //FIXME: implement clearConsoleInt() 695222Sksewell@umich.edu io->clearIntr(0x10/*HW4*/); 705222Sksewell@umich.edu} 715222Sksewell@umich.edu 725222Sksewell@umich.eduvoid 735222Sksewell@umich.eduMalta::postPciInt(int line) 745222Sksewell@umich.edu{ 756379Sgblack@eecs.umich.edu panic("Malta::postPciInt() has not been implemented."); 765222Sksewell@umich.edu} 775222Sksewell@umich.edu 785222Sksewell@umich.eduvoid 795222Sksewell@umich.eduMalta::clearPciInt(int line) 805222Sksewell@umich.edu{ 816379Sgblack@eecs.umich.edu panic("Malta::clearPciInt() has not been implemented."); 825222Sksewell@umich.edu} 835222Sksewell@umich.edu 845222Sksewell@umich.eduAddr 855222Sksewell@umich.eduMalta::pciToDma(Addr pciAddr) const 865222Sksewell@umich.edu{ 876379Sgblack@eecs.umich.edu panic("Malta::pciToDma() has not been implemented."); 885222Sksewell@umich.edu} 895222Sksewell@umich.edu 905222Sksewell@umich.eduvoid 9110905Sandreas.sandberg@arm.comMalta::serialize(CheckpointOut &cp) const 925222Sksewell@umich.edu{ 935222Sksewell@umich.edu SERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs); 945222Sksewell@umich.edu} 955222Sksewell@umich.edu 965222Sksewell@umich.eduvoid 9710905Sandreas.sandberg@arm.comMalta::unserialize(CheckpointIn &cp) 985222Sksewell@umich.edu{ 995222Sksewell@umich.edu UNSERIALIZE_ARRAY(intr_sum_type, Malta::Max_CPUs); 1005222Sksewell@umich.edu} 1015222Sksewell@umich.edu 1025222Sksewell@umich.eduMalta * 1035222Sksewell@umich.eduMaltaParams::create() 1045222Sksewell@umich.edu{ 1055222Sksewell@umich.edu return new Malta(this); 1065222Sksewell@umich.edu} 107