Searched hist:2009 (Results 176 - 200 of 951) sorted by relevance
/gem5/src/python/m5/ | ||
H A D | core.py | diff 6001:00251eb95de7 Thu Mar 05 22:09:00 EST 2009 Nathan Binkert <nate@binkert.org> stats: create an enable phase, and a prepare phase. Enable more or less takes the place of check, but also allows stats to do some other configuration. Prepare moves all of the code that readies a stat for dumping into a separate function in preparation for supporting serialization of certain pieces of statistics data. While we're at it, clean up the visitor code and some of the python code. diff 5860:68c52fee5a53 Wed Feb 04 19:26:00 EST 2009 Nathan Binkert <nate@binkert.org> some new files are missing copyright notices 5801:e0850da03cd4 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> python: Try to isolate the stuff that's in the m5.internal package a bit more. |
/gem5/src/mem/slicc/ast/ | ||
H A D | LiteralExprAST.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
H A D | VarExprAST.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
H A D | TransitionDeclAST.py | diff 6778:b3f2dfbe8006 Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: slicc state machine error fixes Added error messages when: - a state does not exist in a machine's list of known states. - an event does not exist in a machine - the actions of a certain machine have not been declared 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
H A D | DeclListAST.py | diff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons Right now .cc and .hh files are handled separately, but then they're just munged together at the end by scons, so it doesn't buy us anything. Might as well munge from the start since we'll eventually be adding generated Python files to the list too. 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/src/mem/slicc/symbols/ | ||
H A D | __init__.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/src/arch/power/isa/ | ||
H A D | bitfields.isa | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/arch/power/isa/formats/ | ||
H A D | integer.isa | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/arch/sparc/ | ||
H A D | nativetrace.hh | 6365:a3037fa327a0 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Separate out native trace into ISA (in)dependent code and SimObjects. |
/gem5/src/arch/x86/isa/insts/general_purpose/flags/ | ||
H A D | load_and_store.py | diff 6460:59108c231208 Wed Aug 05 06:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use the new forced folding mechanism for the SAHF and LAHF instructions. |
H A D | set_and_clear.py | diff 6062:2116d308076f Sun Apr 19 06:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Explicitly use the right width in a few places that need a 64 bit value. |
/gem5/src/arch/x86/ | ||
H A D | nativetrace.hh | 6365:a3037fa327a0 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Separate out native trace into ISA (in)dependent code and SimObjects. |
/gem5/src/arch/mips/bare_iron/ | ||
H A D | system.cc | diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes. White space, commented out code, some other minor fixes. |
/gem5/src/arch/x86/insts/ | ||
H A D | micromediaop.cc | 6515:a785733109e7 Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Create base classes for use with media/SIMD microops. |
/gem5/src/base/ | ||
H A D | atomicio.cc | diff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned |
H A D | cp_annotate.hh | diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh diff 6002:7d75f1a525db Sat Mar 07 17:30:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix errors for compilers other than g++ 4.3 5952:c1ee8282291d Thu Feb 26 19:29:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> CPA: Add new object for gathering critical path annotations. |
/gem5/src/mem/protocol/ | ||
H A D | SConscript | diff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons Right now .cc and .hh files are handled separately, but then they're just munged together at the end by scons, so it doesn't buy us anything. Might as well munge from the start since we'll eventually be adding generated Python files to the list too. diff 6713:4b6fb0a99039 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: whack some of Nate's leftover debug code diff 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc diff 6655:380a32b43336 Tue Sep 22 18:24:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access diff 6466:4e66dd2decd7 Tue Aug 04 01:42:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> slicc: generate html by default diff 6287:d60118c43d60 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: update parser.py for changes in slicc language. diff 6286:40b142645016 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: update SCons files for changes in ruby. diff 6168:ba6fe02228db Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: add RUBY sticky option that must be set to add ruby to the build Default is false 6157:eaf2fd8f54c0 Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Migrate all of ruby and slicc to SCons. Add the PROTOCOL sticky option sets the coherence protocol that slicc will parse and therefore ruby will use. This whole process was made difficult by the fact that the set of files that are output by slicc are not easily known ahead of time. The easiest thing wound up being to write a parser for slicc that would tell me. Incidentally this means we now have a slicc grammar written in python. |
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/ | ||
H A D | move.py | diff 6733:16817406af29 Tue Nov 10 11:29:00 EST 2009 Vince Weaver <vince@csl.cornell.edu> X86: Fix bugs in movd implementation. Unfortunately my implementation of the movd instruction had two bugs. In one case, when moving a 32-bit value into an xmm register, the lower half of the xmm register was not zero extended. The other case is that xmm was used instead of xmmlm as the source for a register move. My test case didn't notice this at first as it moved xmm0 to eax, which both have the same register number. diff 6706:ea20065f6614 Fri Oct 30 15:52:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> X86: Implement movd_Vo_Edp on X86 This patch implements the movd_Vo_Edp series of instructions. It addresses various concerns by Gabe Black about which file the instruction belonged in, as well as supporting REX prefixed instructions properly. This instruction is needed for some of the spec2k benchmarks, most notably bzip2. diff 6610:dbfe22c711d5 Mon Aug 17 23:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement MOVNTI. diff 6051:47a52383002b Sun Apr 19 06:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the mov to segment selector in real mode instruction microcode. diff 5974:9ed073dd5214 Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set address size to 64 bits when generating addresses internally. diff 5934:367ac7cae7b5 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make rdcr use merge and the mov to control register instructions use the right operand size. diff 5931:d42d507ccdb1 Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the mov to debug register intructions. diff 5928:410d14f82f13 Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a few bugs with the segment register instructions in real mode. Fix a few instances where the register form of zext was used where zexti was intended. Also get rid of the 64 bit only rip relative addressed version since 64 bit and real mode are mutually exclusive. diff 5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop. |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | RubySlicc_includes.hh | diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including. This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol. 6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. |
/gem5/src/arch/alpha/ | ||
H A D | SConsopts | diff 6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants diff 5863:f73e06bc8765 Mon Feb 09 23:10:00 EST 2009 Nathan Binkert <nate@binkert.org> scons: Require SCons version 0.98.1 This allows me to clean things up so we are up to date with respect to deprecated features. There are many features scheduled for permanent failure in scons 2.0 and 0.98.1 provides the most compatability for that. It also paves the way for some nice new features that I will add soon |
/gem5/src/arch/x86/bios/ | ||
H A D | acpi.hh | diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh |
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/ | ||
H A D | increment_and_decrement.py | diff 6092:e4ffbb3546fa Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of DEC. diff 6091:d430acd6d5ce Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of INC. |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/ | ||
H A D | horizontal_addition.py | diff 6799:36131e4dfb6e Sat Dec 19 04:47:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Create a common flag with a name to indicate scalar media instructions. diff 6705:3c810b64ee7d Fri Oct 30 14:19:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> X86: Implement the X86 sse2 haddpd instruction This patch implements the haddpd instruction. It fixes the problem in the previous version (pointed out by Gabe Black) where an incorrect result would happen if you issue the instruction with the same argument twice, i.e. "haddpd %xmm0,%xmm0" This instruction is used by many spec2k benchmarks. |
/gem5/src/dev/x86/ | ||
H A D | pc.cc | diff 6658:f4de76601762 Wed Sep 23 11:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh diff 6073:d552a9544974 Sun Apr 19 07:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Mask the PIC at startup to avoid a glitch which causes an NMI. diff 5844:144524795dfe Sun Feb 01 03:27:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement pciToDma. diff 5843:a2c317cefcf8 Sun Feb 01 03:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Configure the first PCI interrupt. diff 5842:1349786dd9a7 Sun Feb 01 03:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Hook up the IDE controller interrupt line. diff 5834:b9e30a60dee4 Sun Feb 01 03:02:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Devices: Add support for legacy fixed IO locations in BARs. diff 5830:1758d56964c9 Sun Feb 01 02:56:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up the console interrupt and add some DPRINTFs. diff 5829:2fdbb27f8c70 Sun Feb 01 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Configure the IO APIC more. |
/gem5/src/arch/arm/linux/ | ||
H A D | process.hh | diff 6701:4842482e1bd1 Fri Oct 30 03:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Syscalls: Make system calls access arguments like a stack, not an array. When accessing arguments for a syscall, the position of an argument depends on the policies of the ISA, how much space preceding arguments took up, and the "alignment" of the index for this particular argument into the number of possible storate locations. This change adjusts getSyscallArg to take its index parameter by reference instead of value and to adjust it to point to the possible location of the next argument on the stack, basically just after the current one. This way, the rules for the new argument can be applied locally without knowing about other arguments since those have already been taken into account implicitly. All system calls have also been changed to reflect the new interface. In a number of cases this made the implementation clearer since it encourages arguments to be collected in one place in order and then used as necessary later, as opposed to scattering them throughout the function or using them in place in long expressions. It also discourages using getSyscallArg over and over to retrieve the same value when a temporary would do the job. diff 6236:9c0f2130478b Wed Jun 10 02:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params. diff 6233:014ae6da6c2a Wed Jun 10 02:39:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Implement TLS. This is not tested. diff 6232:e0ea733d2105 Wed Jun 10 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make ArmLinuxProcess understand "ARM private" system calls. 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
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