Searched hist:2008 (Results 426 - 450 of 494) sorted by relevance
| /gem5/src/arch/sparc/ | ||
| H A D | process.cc | diff 5771:f58d82cb8b7f Sun Dec 07 15:07:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> imported patch aux-fix.patch diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. |
| H A D | process.hh | diff 5758:9c3edb28db1a Thu Dec 04 18:03:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them. |
| /gem5/src/mem/cache/tags/ | ||
| H A D | fa_lru.cc | diff 5717:6ed48cba2217 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> decouple eviction from insertion in the cache. diff 5716:ee56bb539212 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used. diff 5706:2cc2387049bc Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> probe function no longer used anywhere. |
| /gem5/src/dev/ | ||
| H A D | io_device.cc | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5539:6a27bc3fc267 Tue Aug 26 02:37:00 EDT 2008 Clint Smullen <cws3k@cs.virginia.edu> Device: Fix bug in DmaPort::recvRetry. The interface attempts to send the same packet again. It doesn't cause a problem currently, however with a different Memory Object it could cause problems diff 5534:9eaf72819836 Wed Aug 13 17:41:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Add the ability for a DMA to tack on an extra delay after the DMA is actually finished. |
| /gem5/tests/configs/ | ||
| H A D | tsunami-simple-atomic-dual.py | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
| H A D | tsunami-simple-atomic.py | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
| H A D | tsunami-simple-timing.py | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
| /gem5/src/arch/mips/ | ||
| H A D | types.hh | diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code. |
| /gem5/src/base/loader/ | ||
| H A D | symtab.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
| /gem5/src/arch/x86/ | ||
| H A D | faults.cc | diff 5681:54c2d92f601e Mon Oct 13 01:42:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the x86 interrupt fault kick off the interrupt microcode. |
| H A D | process.hh | diff 5758:9c3edb28db1a Thu Dec 04 18:03:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them. |
| /gem5/src/sim/ | ||
| H A D | byteswap.hh | diff 5549:ed9b39dce0aa Fri Sep 19 12:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> We're using the static keyword improperly in some cases. |
| H A D | system.hh | diff 5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending on the order in which it's registered with the system. To make them match, here is a little change. diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
| H A D | syscall_emul.cc | diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5521:123049ae8ae5 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> syscall: Avoid a compiler warning which turns into a bug. Simply cast the result to an int and life is good. diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. |
| /gem5/src/unittest/ | ||
| H A D | SConscript | 5584:e08e65fd0f76 Thu Oct 02 14:27:00 EDT 2008 Nathan Binkert <nate@binkert.org> unittest: Add unit tests to the scons framework. Also fix the unit tests so they actually compile correctly. |
| /gem5/src/mem/cache/prefetch/ | ||
| H A D | base.hh | 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
| /gem5/src/cpu/o3/ | ||
| H A D | lsq_unit.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5386:5614618f4027 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Don't FastAlloc MSHRs since we don't allocate them on the fly. diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function |
| H A D | inst_queue_impl.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function diff 5327:3390941f0643 Mon Jan 14 11:47:00 EST 2008 Ke Meng <mengke97@hotmail.com> The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state. Signed-off by: Ali Saidi <saidi@eecs.umich.edu> |
| H A D | fetch.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak. diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports. Force all non-default ports to provide a name and an owner in the constructor. |
| H A D | thread_state.hh | diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
| H A D | iew.hh | diff 5557:03c186e416aa Fri Sep 26 10:44:00 EDT 2008 Kevin Lim <ktlim@umich.edu> O3CPU: Fix thread writeback logic. Fix the logic in the LSQ that determines if there are any stores to write back. In the commit stage, check for thread specific writebacks instead of just any writeback. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
| /gem5/src/arch/riscv/ | ||
| H A D | registers.hh | diff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/mem/cache/ | ||
| H A D | base.hh | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
| /gem5/src/base/ | ||
| H A D | statistics.cc | diff 5599:5bad83cddb8c Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> stats: use properly signed types for looping and comparison |
| /gem5/src/python/m5/stats/ | ||
| H A D | __init__.py | diff 10169:628ed23d37af Mon Feb 10 19:24:00 EST 2014 Curtis Dunham <Curtis.Dunham@arm.com> stats: better error message for uninitialized statistic As suggested by Nathan Binkert in 2008: http://permalink.gmane.org/gmane.comp.emulators.m5.users/2676 |
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