Searched hist:2008 (Results 326 - 350 of 494) sorted by relevance
/gem5/src/arch/alpha/ | ||
H A D | types.hh | diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code. diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. |
H A D | isa_traits.hh | diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | system.hh | diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. |
/gem5/src/arch/mips/ | ||
H A D | SConscript | diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. diff 5403:92d376c98a41 Tue May 20 14:04:00 EDT 2008 Stephen Hines <hines@cs.fsu.edu> SCons: Fixing SCons bug 2006 issues for non-alpha ISAs |
H A D | isa_traits.hh | diff 5585:45233156c3cc Mon Oct 06 02:07:00 EDT 2008 Korey Sewell <ksewell@umich.edu> fix shadow set bugs in MIPS code that caused out of bounds access... panic rdpgpr/wrpgpr instructions until a better impl. of MIPS shadow sets is available. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | mt.hh | diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. diff 5561:eb5664be6075 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> Use logical operator instead of bitwise operator for correctness. |
H A D | stacktrace.hh | diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. |
/gem5/src/arch/sparc/ | ||
H A D | remote_gdb.cc | diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | utility.cc | diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. diff 5498:2af99511ded4 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Change everything to use the cached virtPort rather than created their own each time. This appears to work, but I don't want to commit it until it gets tested a lot more. I haven't deleted the functionality in this patch that will come later, but one question is how to enforce encourage objects that call getVirtPort() to not cache the virtual port since if the CPU changes out from under them it will be worse than useless. Perhaps a null function like delVirtPort() is still useful in that case. |
H A D | stacktrace.hh | diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. |
/gem5/src/sim/ | ||
H A D | init.cc | diff 5601:1acb7016d0e4 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> SCons: add code to provide a libm5 shared library. Targets look like libm5_debug.so. This target can be dynamically linked into another C++ program and provide just about all of the M5 features. Additionally, this library is a standalone module that can be imported into python with an "import libm5_debug" type command line. 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. |
/gem5/util/ | ||
H A D | style.py | diff 5747:ffded3077c63 Sat Nov 15 00:21:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> Remove the pointless, repository destroying assertion and just have the script check every line in the file if it cannot get context information. diff 5465:4cff095bbf2b Sat Jun 14 22:37:00 EDT 2008 Nathan Binkert <nate@binkert.org> Add hg commands for style check so you can check at times other than commit |
/gem5/src/cpu/o3/ | ||
H A D | free_list.hh | diff 5364:66d1251b7ae6 Wed Feb 27 17:50:00 EST 2008 Korey Sewell <ksewell@umich.edu> Add comments in code to describe bug conditions. This should help if somebody gets to the bug fix before me (or someone else)... diff 5362:0adba9a562c9 Wed Feb 27 16:48:00 EST 2008 Korey Sewell <ksewell@umich.edu> Fix offset in removeThread() function so that float registers start freeing up from the right point (#32 usually) instead of restarting at 0 and double-freeing. Commented out assert line in free_list.hh that will check for when double-free condition goes bad. |
/gem5/src/arch/sparc/solaris/ | ||
H A D | process.cc | diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. |
/gem5/src/base/loader/ | ||
H A D | object_file.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5 |
/gem5/src/cpu/ | ||
H A D | thread_context.cc | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
H A D | quiesce_event.hh | diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function |
H A D | cpuevent.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. |
/gem5/src/mem/ | ||
H A D | tport.hh | diff 5740:983b71bfc1bd Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> Clean up the SimpleTimingPort class a little bit. Move the constructor into the .cc file and get rid of the typedef for SendEvent. diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. |
/gem5/src/base/ | ||
H A D | time.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | cprintf.hh | diff 5756:88038cdbb9e1 Wed Dec 03 07:57:00 EST 2008 Nathan Binkert <nate@binkert.org> cprintf: support a configurable width and precision ("*" in printf) |
/gem5/src/dev/ | ||
H A D | platform.hh | diff 5478:ca055528a3b3 Tue Jun 17 23:29:00 EDT 2008 Nathan Binkert <nate@binkert.org> Rename SimConsole to Terminal since it makes more sense |
/gem5/src/dev/alpha/ | ||
H A D | tsunami.cc | diff 5478:ca055528a3b3 Tue Jun 17 23:29:00 EDT 2008 Nathan Binkert <nate@binkert.org> Rename SimConsole to Terminal since it makes more sense |
/gem5/src/arch/sparc/isa/formats/mem/ | ||
H A D | swap.isa | diff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request |
/gem5/src/arch/riscv/isa/ | ||
H A D | includes.isa | diff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
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