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| /gem5/src/dev/arm/ | ||
| H A D | gic_v3_cpu_interface.cc | diff 14245:0c0a6fd47628 Mon Aug 26 04:55:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | miscregs.cc | diff 14245:0c0a6fd47628 Mon Aug 26 04:55:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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