Searched hist:12538 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/arch/arm/insts/ | ||
| H A D | misc64.hh | diff 12538:001ad6b1e592 Wed Feb 14 12:45:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | misc64.cc | diff 12538:001ad6b1e592 Wed Feb 14 12:45:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/templates/ | ||
| H A D | misc64.isa | diff 12538:001ad6b1e592 Wed Feb 14 12:45:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | misc64.isa | diff 12538:001ad6b1e592 Wed Feb 14 12:45:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | aarch64.isa | diff 12538:001ad6b1e592 Wed Feb 14 12:45:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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