Searched hist:12445 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/systemc/core/ | ||
| H A D | process.cc | diff 13133:41d8cd260825 Thu Aug 30 03:39:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Keep track of more cases when we should be ready after resume. If a thread self suspends, it should be marked as ready after resuming. If a process was already ready when suspended, it should also be remarked as ready after resuming. Special care has to be taken in pre-initialization situations so that processes are put on the right lists, and whether a process is tracked is already marked as ready. Change-Id: I15da7d747db591785358d47781297468c5f9fd09 Reviewed-on: https://gem5-review.googlesource.com/c/12445 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.hh | diff 13133:41d8cd260825 Thu Aug 30 03:39:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Keep track of more cases when we should be ready after resume. If a thread self suspends, it should be marked as ready after resuming. If a process was already ready when suspended, it should also be remarked as ready after resuming. Special care has to be taken in pre-initialization situations so that processes are put on the right lists, and whether a process is tracked is already marked as ready. Change-Id: I15da7d747db591785358d47781297468c5f9fd09 Reviewed-on: https://gem5-review.googlesource.com/c/12445 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.cc | diff 13133:41d8cd260825 Thu Aug 30 03:39:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Keep track of more cases when we should be ready after resume. If a thread self suspends, it should be marked as ready after resuming. If a process was already ready when suspended, it should also be remarked as ready after resuming. Special care has to be taken in pre-initialization situations so that processes are put on the right lists, and whether a process is tracked is already marked as ready. Change-Id: I15da7d747db591785358d47781297468c5f9fd09 Reviewed-on: https://gem5-review.googlesource.com/c/12445 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | decoder.isa | diff 12445:cda4ad06d1ff Fri Dec 08 18:29:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Fix floating-poing op classes This patch applies correct miscellaneous or multiply-accumulate op classes to floating point instructions which had previously been incorrectly classed as add or multiply instructions. Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb Reviewed-on: https://gem5-review.googlesource.com/6521 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
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