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| H A D | misc.cc | diff 12281:90315832cb81 Wed Nov 15 10:27:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix MCR/MRC disassemble This patch is fixing the Aarch32 MCR/MRC disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the coprocessor register name Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5862 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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