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/gem5/src/cpu/testers/traffic_gen/
H A Dstream_gen.cc12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
H A Dstream_gen.hh12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
H A DBaseTrafficGen.pydiff 12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
H A DSConscriptdiff 12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
H A Dbase.ccdiff 12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
H A Dbase.hhdiff 12919:ddba3d442656 Fri Jul 20 06:23:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> cpu: Stream/SubstreamID support in TrafficGen

This patch is adding support for generating memory requests which set
the StreamID/SubstreamID field, so that is possible to emulate devices
attached to an external IOMMU/SMMU with a Traffic generator.

Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12188
/gem5/src/sim/probe/
H A Dmem.hhdiff 12188:426168f1ba0d Fri Sep 01 07:22:00 EDT 2017 Gabe Black <gabeblack@google.com> mem: Record the request master ID in the PacketInfo structure.

That can be recorded in a packet trace.

Change-Id: I3813ab4ea5aadeb40b355ff01f10e8ecab2bb790
Reviewed-on: https://soc-sim-internal-review.googlesource.com/3482
Reviewed-by: Rahul Thakur <rjthakur@google.com>
Reviewed-on: https://gem5-review.googlesource.com/4780
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

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