/gem5/src/arch/arm/insts/ |
H A D | vfp.hh | 162 } val; local 174 } val; local 186 } val; local 198 } val; local 205 isSnan(fpType val) argument 246 lowFromDouble(double val) argument 252 highFromDouble(double val) argument 265 vfpFpToFixed(T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode = true, VfpRoundingMode roundMode = VfpRoundZero, bool aarch64 = false) argument 766 T val; local [all...] |
/gem5/src/arch/arm/ |
H A D | process.cc | 523 ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 530 ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument [all...] |
H A D | faults.hh | 220 virtual void annotate(AnnotationIDs id, uint64_t val) {} argument
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H A D | types.hh | 239 set(Addr val) argument 245 PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), argument 256 illegalExec(bool val) argument 268 thumb(bool val) argument 283 nextThumb(bool val) argument 308 jazelle(bool val) argument 323 nextJazelle(bool val) argument 338 aarch64(bool val) argument 353 nextAArch64(bool val) argument 432 instNPC(Addr val) argument 451 instIWNPC(Addr val) argument 481 instAIWNPC(Addr val) argument [all...] |
/gem5/src/cpu/o3/ |
H A D | cpu.cc | 1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument 1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument 1267 FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) argument 1275 FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) argument 1283 FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) argument 1291 setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) argument 1299 setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) argument 1308 setCCReg(PhysRegIdPtr phys_reg, RegVal val) argument 1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument 1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument 1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument 1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument 1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument 1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument 1469 pcState(const TheISA::PCState &val, ThreadID tid) argument [all...] |
H A D | cpu.hh | 398 setVecLane(PhysRegIdPtr phys_reg, const LD& val) argument 446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument [all...] |
/gem5/src/dev/arm/ |
H A D | gic_v3_its.cc | 972 const uint64_t val = pkt->getLE<uint64_t>() & w_mask; local
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H A D | gic_v3_cpu_interface.cc | 734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) argument 1768 generateSGI(RegVal val, Gicv3::GroupId group) argument [all...] |
/gem5/src/arch/x86/ |
H A D | process.cc | 1078 X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument 1111 I386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val) argument
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/gem5/src/sim/ |
H A D | syscall_emul.hh | 343 int val = process->getSyscallArg(tc, index); local
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H A D | syscall_emul.cc | 1708 union val { union 1713 } val; local
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/gem5/ext/pybind11/include/pybind11/ |
H A D | pytypes.h | 527 static void set(handle obj, handle key, handle val) { setattr(obj, key, val); } argument 533 static void set(handle obj, const char *key, handle val) { setattr(obj, key, val); } argument 545 static void set(handle obj, handle key, handle val) { argument 559 static void set(handle obj, size_t index, handle val) { argument 576 static void set(handle obj, size_t index, handle val) { argument 593 set(handle obj, size_t index, handle val) argument [all...] |
/gem5/src/cpu/ |
H A D | base_dyn_inst.hh | 671 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) argument 677 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) argument 691 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) argument 697 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) argument 683 setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer& val) argument 703 setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer& val) argument 874 pcState(const TheISA::PCState &val) argument 890 setPredicate(bool val) argument 906 setMemAccPredicate(bool val) argument [all...] |
/gem5/ext/googletest/googletest/test/ |
H A D | gtest_unittest.cc | 5162 operator <<(std::ostream& os, const Base& val) argument 5186 operator <<(std::ostream& os, const MyTypeInUnnamedNameSpace& val) argument 5211 operator <<(std::ostream& os, const MyTypeInNameSpace1& val) argument 5237 operator <<(std::ostream& os, const namespace2::MyTypeInNameSpace2& val) argument
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/gem5/src/arch/x86/regs/ |
H A D | misc.hh | 771 Bitfield<63> val; // Valid member in namespace:X86ISA
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