| /gem5/src/arch/riscv/ |
| H A D | interrupts.hh | 57 BaseCPU * cpu; member in class:RiscvISA::Interrupts
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| /gem5/src/arch/sparc/ |
| H A D | isa.cc | 685 BaseCPU *cpu = NULL; local
771 BaseCPU *cpu = NULL; local
[all...] |
| H A D | interrupts.hh | 61 BaseCPU * cpu; member in class:SparcISA::Interrupts
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| /gem5/src/cpu/o3/ |
| H A D | rob.hh | 271 O3CPU *cpu; member in class:ROB
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| H A D | decode.hh | 212 O3CPU *cpu; member in class:DefaultDecode
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| /gem5/src/cpu/minor/ |
| H A D | decode.cc | 109 dynInstAddTracing(MinorDynInstPtr inst, StaticInstPtr static_inst, MinorCPU &cpu) argument
[all...] |
| H A D | fetch2.hh | 65 MinorCPU &cpu; member in class:Minor::Fetch2
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| H A D | execute.hh | 72 MinorCPU &cpu; member in class:Minor::Execute
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| H A D | fetch1.hh | 72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : argument
192 MinorCPU &cpu; member in class:Minor::Fetch1
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| /gem5/src/dev/arm/ |
| H A D | gic_v3.cc | 189 Gicv3::sendPPInt(uint32_t int_id, uint32_t cpu) argument
200 Gicv3::clearPPInt(uint32_t num, uint32_t cpu) argument
205 Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type) argument
211 Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type) argument
[all...] |
| H A D | generic_timer.cc | 315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) argument
421 GenericTimer::readMiscReg(int reg, unsigned cpu) argument
|
| /gem5/src/gpu-compute/ |
| H A D | dispatcher.hh | 84 BaseCPU *cpu; member in class:GpuDispatcher
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| H A D | shader.cc | 132 Shader::hostWakeUp(BaseCPU *cpu) { argument
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| H A D | dispatcher.cc | 355 GpuDispatcher::accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off) argument
[all...] |
| /gem5/src/cpu/simple/ |
| H A D | atomic.hh | 152 BaseSimpleCPU *cpu; member in class:AtomicSimpleCPU::AtomicCPUDPort
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| H A D | timing.hh | 112 TimingSimpleCPU *cpu; member in class:TimingSimpleCPU::FetchTranslation
171 TimingSimpleCPU* cpu; member in class:TimingSimpleCPU::TimingCPUPort
176 TimingSimpleCPU *cpu; member in struct:TimingSimpleCPU::TimingCPUPort::TickEvent
331 TimingSimpleCPU *cpu; member in struct:TimingSimpleCPU::IprEvent
[all...] |
| H A D | exec_context.hh | 67 BaseSimpleCPU *cpu; member in class:SimpleExecContext
[all...] |
| /gem5/src/dev/sparc/ |
| H A D | iob.hh | 92 int cpu; member in struct:Iob::IntMan
|
| /gem5/src/arch/arm/kvm/ |
| H A D | gic.cc | 257 MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu) argument
266 MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu) argument
[all...] |
| /gem5/src/cpu/o3/probe/ |
| H A D | elastic_trace.hh | 377 FullO3CPU<O3CPUImpl>* cpu; member in class:ElasticTrace
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| /gem5/src/arch/arm/ |
| H A D | interrupts.hh | 62 BaseCPU * cpu; member in class:ArmISA::Interrupts
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| /gem5/tests/configs/ |
| H A D | gpu-ruby.py | 252 cpu = TimingSimpleCPU(cpu_id=0) variable
[all...] |
| /gem5/src/arch/mips/ |
| H A D | utility.cc | 222 zeroRegisters(CPU *cpu) argument
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| /gem5/src/cpu/kvm/ |
| H A D | base.hh | 598 BaseKvmCPU *cpu; member in class:BaseKvmCPU::KVMCpuPort
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| /gem5/src/arch/x86/ |
| H A D | interrupts.hh | 170 BaseCPU *cpu; member in class:X86ISA::Interrupts
|