| /gem5/src/cpu/o3/ |
| H A D | commit_impl.hh | 134 DefaultCommit<Impl>::name() const argument
407 DefaultCommit<Impl>::drainSanityCheck() const argument
415 DefaultCommit<Impl>::isDrained() const argument
[all...] |
| H A D | lsq_unit_impl.hh | 88 LSQUnit<Impl>::WritebackEvent::description() const argument
195 LSQUnit<Impl>::name() const argument
258 LSQUnit<Impl>::drainSanityCheck() const argument
1107 dumpInsts() const argument
[all...] |
| H A D | iew_impl.hh | 119 DefaultIEW<Impl>::name() const argument
396 DefaultIEW<Impl>::isDrained() const argument
425 DefaultIEW<Impl>::drainSanityCheck() const argument
[all...] |
| H A D | lsq_impl.hh | 115 LSQ<Impl>::name() const argument
140 LSQ<Impl>::drainSanityCheck() const argument
150 LSQ<Impl>::isDrained() const argument
193 LSQ<Impl>::cacheBlocked() const argument
207 LSQ<Impl>::cachePortAvailable(bool is_load) const argument
514 LSQ<Impl>::isEmpty() const argument
521 lqEmpty() const argument
538 sqEmpty() const argument
674 dumpInsts() const argument
[all...] |
| /gem5/src/dev/net/ |
| H A D | ns_gige.cc | 924 NSGigE::cpuIntrPending() const argument
2020 NSGigE::serialize(CheckpointOut &cp) const argument
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| H A D | sinic.cc | 587 Base::cpuIntrPending() const argument
1230 serialize(CheckpointOut &cp) const argument
1275 serialize(CheckpointOut &cp) const argument
[all...] |
| /gem5/src/dev/virtio/ |
| H A D | base.hh | 162 Index index() const { return _index; } argument
231 size_t size() const { return desc.len; } argument
238 bool hasNext() const { return desc.flags & VRING_DESC_F_NEXT; } argument
248 bool isIncoming() const { return !isOutgoing(); } argument
250 bool isOutgoing() const { retur argument
341 getAddress() const argument
348 getSize() const argument
774 getQueueSelect() const argument
812 getQueueSize() const argument
829 getDeviceStatus() const argument
844 getGuestFeatures() const argument
[all...] |
| /gem5/src/arch/arm/ |
| H A D | pagetable.hh | 64 void serialize(CheckpointOut &cp) const argument
187 pageStart() const argument
222 checkELMatch(ExceptionLevel target_el) const argument
232 pAddr(Addr va) const argument
287 print() const argument
193 match(Addr va, uint8_t _vmid, bool hypLookUp, bool secure_lookup, ExceptionLevel target_el) const argument
200 match(Addr va, uint16_t asn, uint8_t _vmid, bool hypLookUp, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el) const argument
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| /gem5/src/mem/cache/ |
| H A D | cache.cc | 480 createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needsWritable, bool is_whole_line_write) const argument
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| /gem5/src/sim/ |
| H A D | process.cc | 355 Process::serialize(CheckpointOut &cp) const argument
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| /gem5/src/cpu/pred/ |
| H A D | tage_base.cc | 202 TAGEBase::bindex(Addr pc_in) const argument
208 TAGEBase::F(int A, int size, int bank) const argument
225 TAGEBase::gindex(ThreadID tid, Addr pc, int bank) const argument
243 TAGEBase::gtag(ThreadID tid, Addr pc, int bank) const argument
288 TAGEBase::getBimodePred(Addr pc, BranchInfo* bi) const argument
704 getGHR(ThreadID tid, BranchInfo *bi) const argument
783 getCtr(int hitBank, int hitBankIndex) const argument
789 getTageCtrBits() const argument
795 getPathHist(ThreadID tid) const argument
801 isSpeculativeUpdateEnabled() const argument
807 getSizeInBits() const argument
[all...] |
| /gem5/src/cpu/ |
| H A D | reg_class.hh | 108 bool operator==(const RegId& that) const { argument
113 bool operator!=(const RegId& that) const { argument
120 bool operator<(const RegId& that) const { argument
130 bool isRenameable() const argument
141 inline bool isZeroReg() const argument
149 isIntReg() const argument
152 isFloatReg() const argument
155 isVecReg() const argument
158 isVecElem() const argument
161 isVecPredReg() const argument
164 isCCReg() const argument
167 isMiscReg() const argument
179 index() const argument
185 flatIndex() const argument
204 elemIndex() const argument
206 classValue() const argument
208 className() const argument
210 getNumPinnedWrites() const argument
267 operator <(const PhysRegId& that) const argument
271 operator ==(const PhysRegId& that) const argument
275 operator !=(const PhysRegId& that) const argument
281 isIntPhysReg() const argument
284 isFloatPhysReg() const argument
287 isCCPhysReg() const argument
290 isVectorPhysReg() const argument
293 isVectorPhysElem() const argument
296 isVecPredPhysReg() const argument
299 isMiscPhysReg() const argument
305 isFixedMapping() const argument
311 flatIndex() const argument
319 getNumPinnedWrites() const argument
336 isPinned() const argument
338 getNumPinnedWritesToComplete() const argument
359 operator ()(const RegId& reg_id) const argument
[all...] |
| /gem5/src/mem/ |
| H A D | coherent_xbar.cc | 1066 sinkPacket(const PacketPtr pkt) const argument
[all...] |
| H A D | comm_monitor.hh | 72 const Params* params() const argument
161 bool isSnooping() const argument
222 AddrRangeList getAddrRanges() const argument
[all...] |
| /gem5/src/mem/ruby/system/ |
| H A D | GPUCoalescer.hh | 164 int outstandingCount() const { return m_outstanding_count; } argument
167 isDeadlockEventScheduled() const argument
202 getMissMachLatencyHist(uint32_t t) const argument
206 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const argument
209 getIssueToInitialDelayHist(uint32_t t) const argument
213 getInitialToForwardDelayHist(const MachineType t) const argument
217 getForwardRequestToFirstResponseHist(const MachineType t) const argument
221 getFirstResponseToCompletionDelayHist(const MachineType t) const argument
[all...] |
| H A D | Sequencer.cc | 524 empty() const argument
673 print(ostream& out) const argument
[all...] |
| H A D | Sequencer.hh | 88 outstandingCount() const argument
90 isDeadlockEventScheduled() const argument
102 coreId() const argument
126 getMissMachLatencyHist(uint32_t t) const argument
130 getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const argument
133 getIssueToInitialDelayHist(uint32_t t) const argument
137 getInitialToForwardDelayHist(const MachineType t) const argument
141 getForwardRequestToFirstResponseHist(const MachineType t) const argument
145 getFirstResponseToCompletionDelayHist(const MachineType t) const argument
148 getIncompleteTimes(const MachineType t) const argument
[all...] |
| /gem5/src/dev/arm/ |
| H A D | smmu_v3_transl.cc | 236 SMMUTranslationProcess::bypass(Addr addr) const argument
1024 combineTranslations(const TranslResult &s1tr, const TranslResult &s2tr) const argument
[all...] |
| H A D | gic_v3_redistributor.hh | 203 getCPUInterface() const argument
209 processorNumber() const argument
[all...] |
| H A D | gic_v3_distributor.hh | 183 groupEnabled(Gicv3::GroupId group) const argument
218 isNotSPI(uint32_t int_id) const argument
227 nsAccessToSecInt(uint32_t int_id, bool is_secure_access) const argument
[all...] |
| /gem5/src/base/ |
| H A D | statistics.cc | 132 InfoAccess::info() const argument
257 Info::baseCheck() const argument
469 result(VResult &vec) const argument
476 total() const argument
482 size() const argument
496 zero() const argument
507 str() const argument
[all...] |
| /gem5/src/cpu/checker/ |
| H A D | cpu.hh | 455 readMiscRegNoEffect(int misc_reg) const argument
[all...] |
| /gem5/ext/pybind11/include/pybind11/detail/ |
| H A D | internals.h | 84 operator ()(const std::pair<const PyObject *, const char *>& v) const argument
[all...] |
| /gem5/ext/pybind11/tests/ |
| H A D | test_class.cpp | 50 std::string name() const { return m_name; } argument
51 std::string species() const { return m_species; } argument
60 std::string bark() const { return "Woof!"; } argument
258 foo() const argument
282 foo() const argument
364 ptr() const argument
[all...] |
| /gem5/ext/dsent/model/ |
| H A D | Model.cc | 48 const Model* Model::SubModel::getModel() const argument
53 double Model::SubModel::getNumModels() const argument
58 Model::SubModel* Model::SubModel::clone() const argument
126 getInstanceName() const argument
137 getIsTopModel() const argument
163 getParameterNames() const argument
185 getPropertyNames() const argument
190 checkParameters() const argument
206 checkProperties() const argument
226 getParameters() const argument
231 getParameter(const String& parameter_name_) const argument
247 getProperties() const argument
252 getProperty(const String& property_name_) const argument
271 getGenProperties() const argument
311 getSubInstance(const String& sub_instance_name_) const argument
324 hasSubInstance(const String& sub_instance_name_) const argument
351 getAreaResult(const String& area_name_) const argument
356 hasAreaResult(const String& area_name_) const argument
383 getNddPowerResult(const String& ndd_power_name_) const argument
388 hasNddPowerResult(const String& ndd_power_name_) const argument
415 getEventResult(const String& event_name_) const argument
420 hasEventResult(const String& event_name_) const argument
425 getTechModel() const argument
499 queryArea(const String& area_name_) const argument
619 printHierarchy(const String& query_type_, const String& query_sub_field_, const String& prepend_str_, int detail_level_, ostream& ost_) const argument
677 printInstHierarchy(const String& prepend_str_, int detail_level_, ostream& ost_) const argument
693 clone() const argument
[all...] |