switcheroo.py (11682:612f75cf36a0) | switcheroo.py (11802:be62996c95d1) |
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1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38import m5 | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 22 unchanged lines hidden (view full) --- 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38import m5 |
39import _m5 |
|
39from m5.objects import * 40m5.util.addToPath('../configs/') 41from common.Caches import * 42 43class Sequential: 44 """Sequential CPU switcher. 45 46 The sequential CPU switches between all CPUs in a system in --- 52 unchanged lines hidden (view full) --- 99 100 current_cpu = switcher.first() 101 system = root.system 102 system.mem_mode = type(current_cpu).memory_mode() 103 104 # Suppress "Entering event queue" messages since we get tons of them. 105 # Worse yet, they include the timestamp, which makes them highly 106 # variable and unsuitable for comparing as test outputs. | 40from m5.objects import * 41m5.util.addToPath('../configs/') 42from common.Caches import * 43 44class Sequential: 45 """Sequential CPU switcher. 46 47 The sequential CPU switches between all CPUs in a system in --- 52 unchanged lines hidden (view full) --- 100 101 current_cpu = switcher.first() 102 system = root.system 103 system.mem_mode = type(current_cpu).memory_mode() 104 105 # Suppress "Entering event queue" messages since we get tons of them. 106 # Worse yet, they include the timestamp, which makes them highly 107 # variable and unsuitable for comparing as test outputs. |
107 m5.internal.core.cvar.want_info = verbose | 108 _m5.core.cvar.want_info = verbose |
108 109 # instantiate configuration 110 m5.instantiate() 111 112 # Determine the switching period, this has to be done after 113 # instantiating the system since the time base must be fixed. 114 period = m5.ticks.fromSeconds(1.0 / freq) 115 while True: --- 23 unchanged lines hidden --- | 109 110 # instantiate configuration 111 m5.instantiate() 112 113 # Determine the switching period, this has to be done after 114 # instantiating the system since the time base must be fixed. 115 period = m5.ticks.fromSeconds(1.0 / freq) 116 while True: --- 23 unchanged lines hidden --- |