1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37
38import m5
39from m5.objects import *
40m5.util.addToPath('../configs/common')
41from Caches import *
42
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43def _memMode(cclass):
44 if cclass == AtomicSimpleCPU:
45 return "atomic", m5.objects.params.atomic
46 else:
47 return "timing", m5.objects.params.timing
48
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43class Sequential:
44 """Sequential CPU switcher.
45
46 The sequential CPU switches between all CPUs in a system in
47 order. The CPUs in the system must have been prepared for
48 switching, which in practice means that only one CPU is switched
49 in. base_config.BaseFSSwitcheroo can be used to create such a
50 system.
51 """
52 def __init__(self, cpus):
53 self.first_cpu = None
54 for (cpuno, cpu) in enumerate(cpus):
55 if not cpu.switched_out:
56 if self.first_cpu != None:
57 fatal("More than one CPU is switched in");
58 self.first_cpu = cpuno
59
60 if self.first_cpu == None:
61 fatal("The system contains no switched in CPUs")
62
63 self.cur_cpu = self.first_cpu
64 self.cpus = cpus
65
66 def next(self):
67 self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus)
68 return self.cpus[self.cur_cpu]
69
70 def first(self):
71 return self.cpus[self.first_cpu]
72
73def run_test(root, switcher=None, freq=1000):
74 """Test runner for CPU switcheroo tests.
75
76 The switcheroo test runner is used to switch CPUs in a system that
77 has been prepared for CPU switching. Such systems should have
78 multiple CPUs when they are instantiated, but only one should be
79 switched in. Such configurations can be created using the
80 base_config.BaseFSSwitcheroo class.
81
82 A CPU switcher object is used to control switching. The default
83 switcher sequentially switches between all CPUs in a system,
84 starting with the CPU that is currently switched in.
85
86 Unlike most other test runners, this one automatically configures
87 the memory mode of the system based on the first CPU the switcher
88 reports.
89
90 Keyword Arguments:
91 switcher -- CPU switcher implementation. See Sequential for
92 an example implementation.
93 period -- Switching frequency in Hz.
94 """
95
96 if switcher == None:
97 switcher = Sequential(root.system.cpu)
98
99 current_cpu = switcher.first()
100 system = root.system
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107 system.mem_mode = _memMode(type(current_cpu))[0]
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| 101 system.mem_mode = type(current_cpu).memory_mode() |
102
103 # instantiate configuration
104 m5.instantiate()
105
106 # Determine the switching period, this has to be done after
107 # instantiating the system since the time base must be fixed.
108 period = m5.ticks.fromSeconds(1.0 / freq)
109 while True:
110 exit_event = m5.simulate(period)
111 exit_cause = exit_event.getCause()
112
113 if exit_cause == "simulate() limit reached":
114 next_cpu = switcher.next()
115
116 print "Switching CPUs..."
117 print "Next CPU: %s" % type(next_cpu)
118 m5.drain(system)
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125 system.setMemoryMode(_memMode(type(next_cpu))[1])
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119 if current_cpu != next_cpu:
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127 m5.switchCpus([ (current_cpu, next_cpu) ])
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120 m5.switchCpus(system, [ (current_cpu, next_cpu) ],
121 do_drain=False) |
122 else:
123 print "Source CPU and destination CPU are the same, skipping..."
124 m5.resume(system)
125 current_cpu = next_cpu
126 elif exit_cause == "target called exit()" or \
127 exit_cause == "m5_exit instruction encountered":
128
129 sys.exit(0)
130 else:
131 print "Test failed: Unknown exit cause: %s" % exit_cause
132 sys.exit(1)
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